On Thu, Mar 06, 2025 at 04:22:52PM +1000, Alistair Francis wrote:
On Thu, Mar 6, 2025 at 4:13 PM Deepak Gupta wrote:
On Thu, Mar 06, 2025 at 03:29:00PM +1000, Alistair Francis wrote:
>On Tue, Feb 18, 2025 at 12:57 PM Deepak Gupta wrote:
>>
>> Commit f06bfe3dc38c ("target/riscv: implement zicf
On Thu, Mar 6, 2025 at 4:13 PM Deepak Gupta wrote:
>
> On Thu, Mar 06, 2025 at 03:29:00PM +1000, Alistair Francis wrote:
> >On Tue, Feb 18, 2025 at 12:57 PM Deepak Gupta wrote:
> >>
> >> Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
> >> `ssamoswap` instruction. `ssamo
On Thu, Mar 06, 2025 at 03:29:00PM +1000, Alistair Francis wrote:
On Tue, Feb 18, 2025 at 12:57 PM Deepak Gupta wrote:
Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
`ssamoswap` instruction. `ssamoswap` takes the code-point from existing
reserved encoding (and not a
On Tue, Feb 18, 2025 at 12:57 PM Deepak Gupta wrote:
>
> Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
> `ssamoswap` instruction. `ssamoswap` takes the code-point from existing
> reserved encoding (and not a zimop like other shadow stack instructions).
> If shadow stack
Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
`ssamoswap` instruction. `ssamoswap` takes the code-point from existing
reserved encoding (and not a zimop like other shadow stack instructions).
If shadow stack is not enabled (via xenvcfg.SSE), then `ssamoswap` must
result
