On 12/9/21 10:26 PM, Alistair Francis wrote:
@@ -975,7 +975,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG);
target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;
target_ulong deleg = async ? env->mideleg : env-
From: Alistair Francis
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers based on the CPU feature.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h|
