Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default

On Fri, Jul 8, 2022 at 3:39 PM Kito Cheng wrote: > Default ELEN is setting to 64 for now, which is incorrect setting for > Zve32*, and spec has mention minimum VLEN and supported EEW in chapter > "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32. > > ELEN actaully could be derived

Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default

在 2022/7/9 下午4:11, Weiwei Li 写道: 在 2022/7/8 下午3:39, Kito Cheng 写道: Default ELEN is setting to 64 for now, which is incorrect setting for Zve32*, and spec has mention minimum VLEN and supported EEW in chapter "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32. ELEN actaully coul

Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default

在 2022/7/8 下午3:39, Kito Cheng 写道: Default ELEN is setting to 64 for now, which is incorrect setting for Zve32*, and spec has mention minimum VLEN and supported EEW in chapter "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32. ELEN actaully could be derived from which extensions a

[PATCH 2/2] target/riscv: Auto set elen from vector extension by default

Default ELEN is setting to 64 for now, which is incorrect setting for Zve32*, and spec has mention minimum VLEN and supported EEW in chapter "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32. ELEN actaully could be derived from which extensions are enabled, so this patch set elen t