ian Cain ; richard.hender...@linaro.org;
alex.ben...@linaro.org
Subject: RE: [PATCH 2/2] target/hexagon: rename aliased register HEX_REG_P3_0
> -Original Message-
> From: Mukilan Thiyagarajan (QUIC)
> Sent: Tuesday, December 27, 2022 9:35 AM
> To: qemu-devel@nongnu.org; Tayl
n (QUIC)
>
> Subject: [PATCH 2/2] target/hexagon: rename aliased register
> HEX_REG_P3_0
>
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index
> 658ca4ff78..807037c586 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -86,7 +86,7 @@ stati
The patch renames the identifier of the 32bit register
HEX_REG_P3_0 to HEX_REG_P3_0_ALIASED.
This change is to intended to provide some warning that
HEX_REG_P3_0 is an aliased register which has multiple
representations in CPU state and therefore might require
special handling in some contexts. Th
