Re: [PATCH 16/25] target/i386: adapt gen_shift_count for SHLD/SHRD

2024-06-08 Thread Richard Henderson
On 6/8/24 01:41, Paolo Bonzini wrote: SHLD/SHRD can have 3 register operands - s->T0, s->T1 and either 1 or CL - and therefore decode->op[2] is taken by the low part of the register being shifted. Pass X86_OP_* to gen_shift_count from its current callers and hardcode cpu_regs[R_ECX] as the shift

[PATCH 16/25] target/i386: adapt gen_shift_count for SHLD/SHRD

2024-06-08 Thread Paolo Bonzini
SHLD/SHRD can have 3 register operands - s->T0, s->T1 and either 1 or CL - and therefore decode->op[2] is taken by the low part of the register being shifted. Pass X86_OP_* to gen_shift_count from its current callers and hardcode cpu_regs[R_ECX] as the shift count. Signed-off-by: Paolo Bonzini -