On 2021/11/2 上午12:33, Richard Henderson wrote:
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
@@ -2677,6 +2677,7 @@ static bool trans_vmv_s_x(DisasContext *s,
arg_vmv_s_x *a)
/* This instruction ignores LMUL and vector register groups */
int maxsz = s->vlen >> 3;
TCGv_i64
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
@@ -2677,6 +2677,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
/* This instruction ignores LMUL and vector register groups */
int maxsz = s->vlen >> 3;
TCGv_i64 t1;
+TCGv src1 = get_gpr(s, a->rs1, EXT_ZE
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++--
target/riscv/vector_helper.c
