Re: [PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap

Hi Anton, This patch violates some coding style rules of QEMU. You can verify the coding style by running the checkpatch.pl script in the QEMU repository. (ref: https://www.qemu.org/docs/master/devel/submitting-a-patch.html#use-the-qemu-coding-style) The patch 12 also has the same issue. Than

[PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap

for 2*SEW = 2*SEW op SEW instructions vs2 and vs1 cannot overlap because it would mean a register is read with two different SEW settings. Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv