Re: [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations

On Sun, Jul 10, 2022 at 6:25 PM Weiwei Li wrote: > > - There are 3 suggested privilege modes conbinations listed in the spec: > 1) M, 2) M, U 3) M, S, U > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 6 ++ >

[PATCH 1/6] target/riscv: add check for supported privilege modes conbinations

- There are 3 suggested privilege modes conbinations listed in the spec: 1) M, 2) M, U 3) M, S, U Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bb3973806..0dad