Re: [PATCH 1/4] target/riscv: Fix csr number based privilege checking

On Fri, Apr 29, 2022 at 8:20 PM Frank Chang wrote: > Reviewed-by: Frank Chang > > On Fri, Apr 29, 2022 at 11:34 AM Anup Patel > wrote: > >> When hypervisor and VS CSRs are accessed from VS-mode or VU-mode, >> the riscv_csrrw_check() function should generate virtual instruction >> trap instead i

Re: [PATCH 1/4] target/riscv: Fix csr number based privilege checking

Reviewed-by: Frank Chang On Fri, Apr 29, 2022 at 11:34 AM Anup Patel wrote: > When hypervisor and VS CSRs are accessed from VS-mode or VU-mode, > the riscv_csrrw_check() function should generate virtual instruction > trap instead illegal instruction trap. > > Fixes: 533c91e8f22c ("target/riscv:

Re: [PATCH 1/4] target/riscv: Fix csr number based privilege checking

On Fri, Apr 29, 2022 at 1:36 PM Anup Patel wrote: > > When hypervisor and VS CSRs are accessed from VS-mode or VU-mode, > the riscv_csrrw_check() function should generate virtual instruction > trap instead illegal instruction trap. > > Fixes: 533c91e8f22c ("target/riscv: Use RISCVException enum fo

[PATCH 1/4] target/riscv: Fix csr number based privilege checking

When hypervisor and VS CSRs are accessed from VS-mode or VU-mode, the riscv_csrrw_check() function should generate virtual instruction trap instead illegal instruction trap. Fixes: 533c91e8f22c ("target/riscv: Use RISCVException enum for CSR access") Signed-off-by: Anup Patel --- target/riscv/cs