Re: [PATCH 1/2] target/riscv: FIX xATP_MODE validation

Hi Irina, On 2023/12/1 19:53, Irina Ryapolova wrote: The SATP register is an SXLEN-bit read/write WARL register. It means that CSR fields are only defined for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal value whenever read (See riscv-privil

[PATCH 1/2] target/riscv: FIX xATP_MODE validation

The SATP register is an SXLEN-bit read/write WARL register. It means that CSR fields are only defined for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal value whenever read (See riscv-privileged-20211203, SATP CSR). For example on rv64 we are tr