Re: [PATCH 1/2] qpci_device_enable: Allow for command bits hardwired to 0

2022-10-31 Thread Michael S. Tsirkin
On Mon, Oct 24, 2022 at 09:46:20AM +, Lev Kujawski wrote: > Devices like the PIIX3/4 IDE controller do not support certain modes > of operation, such as memory space accesses, and indicate this lack of > support by hardwiring the applicable bits to zero. Extend the QEMU > PCI device testing fr

[PATCH 1/2] qpci_device_enable: Allow for command bits hardwired to 0

2022-10-24 Thread Lev Kujawski
Devices like the PIIX3/4 IDE controller do not support certain modes of operation, such as memory space accesses, and indicate this lack of support by hardwiring the applicable bits to zero. Extend the QEMU PCI device testing framework to accommodate such devices. * tests/qtest/libqos/pci.h: Add

[PATCH 1/2] qpci_device_enable: Allow for command bits hardwired to 0

2022-06-29 Thread Lev Kujawski
Devices like the PIIX3/4 IDE controller do not support certain modes of operation, such as memory space accesses, and indicate this lack of support by hardwiring the applicable bits to zero. The QEMU PCI device testing framework is hereby extended to accommodate such devices. * tests/qtest/libqos/