RE: [PATCH 1/2] Hexagon (iclass): update J4_hintjumpr slot constraints

2023-05-11 Thread Taylor Simpson
> -Original Message- > From: Matheus Tavares Bernardino > Sent: Friday, January 13, 2023 7:39 AM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Brian Cain > ; richard.hender...@linaro.org > Subject: [PATCH 1/2] Hexagon (iclass): update J4_hintjumpr slot constra

RE: [PATCH 1/2] Hexagon (iclass): update J4_hintjumpr slot constraints

2023-01-13 Thread Taylor Simpson
> -Original Message- > From: Matheus Tavares Bernardino > Sent: Friday, January 13, 2023 7:39 AM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Brian Cain > ; richard.hender...@linaro.org > Subject: [PATCH 1/2] Hexagon (iclass): update J4_hintjumpr slot constra

[PATCH 1/2] Hexagon (iclass): update J4_hintjumpr slot constraints

2023-01-13 Thread Matheus Tavares Bernardino
The Hexagon PRM says that "The assembler automatically encodes instructions in the packet in the proper order. In the binary encoding of a packet, the instructions must be ordered from Slot 3 down to Slot 0." Prior to the architecture version v73, the slot constraints from instruction "hintjr" onl