On 2020/7/2 0:25, Richard Henderson wrote:
On 7/1/20 8:21 AM, LIU Zhiwei wrote:
-tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
+tcg_gen_qemu_ld_i32(t1, addr, idx, memop);
+tcg_gen_ext_i32(val, val, memop);
gen(t2, t1, val);
I was just about to post a simiar patch.
T
On 7/1/20 8:21 AM, LIU Zhiwei wrote:
> -tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
> +tcg_gen_qemu_ld_i32(t1, addr, idx, memop);
> +tcg_gen_ext_i32(val, val, memop);
> gen(t2, t1, val);
I was just about to post a simiar patch.
The difference with mine is that I do not m
Reserve MO_SIGN in load and extend another operator val according to memop.
Thus, we can call tcg_gen_atomic_*_tl with a smaller memop.
Signed-off-by: LIU Zhiwei
---
tcg/tcg-op.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index e60b74fb8
