On 9/11/20 6:55 PM, Richard Henderson wrote:
> On 9/11/20 3:41 AM, Peter Maydell wrote:
>>> +/* Detect store by reading the instruction at the program counter. */
>>> +uint32_t insn = *(uint32_t *)pc;
>>> +switch(insn>>29) {
>>> +case 0x5:
>>> +switch((insn>>26) & 0x7) {
>>
On 9/11/20 3:41 AM, Peter Maydell wrote:
>> +/* Detect store by reading the instruction at the program counter. */
>> +uint32_t insn = *(uint32_t *)pc;
>> +switch(insn>>29) {
>> +case 0x5:
>> +switch((insn>>26) & 0x7) {
>
> Here we mask to get a 3-bit field...
>
>> +
On Fri, 11 Sep 2020 at 02:14, zou xu wrote:
>
> From 533ed02427bdaf0265f62fcb4f961854a41b7037 Mon Sep 17 00:00:00 2001
> From: ZouXu
> Date: Wed, 9 Sep 2020 21:59:13 +0800
> Subject: [PATCH 1/1] accel/tcg/user-exec: support computing is_write for
> mips32
>
> Those MIPS3
>From 533ed02427bdaf0265f62fcb4f961854a41b7037 Mon Sep 17 00:00:00 2001
From: ZouXu
Date: Wed, 9 Sep 2020 21:59:13 +0800
Subject: [PATCH 1/1] accel/tcg/user-exec: support computing is_write for
mips32
Those MIPS32 instructions can cause store operation:
SB/SH/SW/SD/SWL/SWR/SDL/SDR/CACHE
SC/
