Re: [PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns

On Wed, Dec 29, 2021 at 12:43 PM wrote: > > From: Frank Chang > > Zve64f extension requires the scalar processor to implement the F > extension and implement all vector floating-point instructions for > floating-point operands with EEW=32 (i.e., no widening floating-point > operations). > > Signe

[PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns

From: Frank Chang Zve64f extension requires the scalar processor to implement the F extension and implement all vector floating-point instructions for floating-point operands with EEW=32 (i.e., no widening floating-point operations). Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans