Re: [PATCH 06/11 v2] target/riscv: Update CSR xtvec in CLIC mode

2024-09-05 Thread Alistair Francis
On Tue, Aug 20, 2024 at 2:15 AM Ian Brockbank wrote: > > From: Ian Brockbank > > The new CLIC interrupt-handling mode is encoded as a new state in the > existing WARL xtvec register, where the low two bits of are 11. > > Signed-off-by: LIU Zhiwei > Signed-off-by: Ian Brockbank > --- > target/r

[PATCH 06/11 v2] target/riscv: Update CSR xtvec in CLIC mode

2024-08-19 Thread Ian Brockbank
From: Ian Brockbank The new CLIC interrupt-handling mode is encoded as a new state in the existing WARL xtvec register, where the low two bits of are 11. Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 2 ++ target/riscv/c