..@rev.ng; Marco
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Brian Cain
>
> Subject: RE: [PATCH 05/39] target/hexagon: Implement modify SSR
>
>
>
> > -Original Message-
> > From: ltaylorsimp...@gmail.com
> > Sent: Monday, March 17
On 3/19/25 09:39, ltaylorsimp...@gmail.com wrote:
I caution against putting a level of indirection into CPUHexagonState for the
HVX registers. The HVX TCG implementation relies on an offset from the start
of CPUHexagonState to identify the operands. This would be a very significant
rewrite i
ev.ng; a...@rev.ng; 'Marco
> Liebel (QUIC)' ; alex.ben...@linaro.org; 'Mark
> Burton (QUIC)' ; 'Brian Cain'
>
> Subject: Re: [PATCH 05/39] target/hexagon: Implement modify SSR
>
>
> On 3/18/2025 2:14 PM, ltaylorsimp...@gmail.com wrote:
> >
(QUIC) ; a...@rev.ng; a...@rev.ng; Marco
Liebel (QUIC) ; alex.ben...@linaro.org; Mark
Burton (QUIC) ; Brian Cain
Subject: RE: [PATCH 05/39] target/hexagon: Implement modify SSR
-Original Message-
From: ltaylorsimp...@gmail.com
Sent: Monday, March 17, 2025 12:37 PM
To: 'Brian Ca
o
> Liebel (QUIC) ; alex.ben...@linaro.org; Mark
> Burton (QUIC) ; Sid Manning
> ; Brian Cain
> Subject: RE: [PATCH 05/39] target/hexagon: Implement modify SSR
>
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and d
c_mlie...@quicinc.com; ltaylorsimp...@gmail.com;
> alex.ben...@linaro.org; quic_mbur...@quicinc.com;
> sidn...@quicinc.com; Brian Cain
> Subject: [PATCH 05/39] target/hexagon: Implement modify SSR
>
> From: Brian Cain
>
> The per-vCPU System Status Register controls many modal behavio
From: Brian Cain
The per-vCPU System Status Register controls many modal behaviors of the
system architecture. When the SSR is updated, we trigger the necessary
effects for interrupts, privilege/MMU, and HVX context mapping.
Signed-off-by: Brian Cain
---
target/hexagon/cpu_helper.c | 100
