Re: [PATCH 02/13] hw/ide/via: Implement ISA IRQ routing

2023-04-26 Thread Mark Cave-Ayland
On 22/04/2023 16:07, Bernhard Beschow wrote: The VIA south bridge allows the legacy IDE interrupts to be routed to four different ISA interrupts. This can be configured through the 0x4a register in the PCI configuration space of the ISA function. The default routing matches the legacy ISA IRQs,

Re: [PATCH 02/13] hw/ide/via: Implement ISA IRQ routing

2023-04-24 Thread BALATON Zoltan
On Mon, 24 Apr 2023, Bernhard Beschow wrote: Am 22. April 2023 19:21:12 UTC schrieb BALATON Zoltan : On Sat, 22 Apr 2023, Bernhard Beschow wrote: Am 22. April 2023 17:23:56 UTC schrieb BALATON Zoltan : On Sat, 22 Apr 2023, Bernhard Beschow wrote: The VIA south bridge allows the legacy IDE int

Re: [PATCH 02/13] hw/ide/via: Implement ISA IRQ routing

2023-04-24 Thread Bernhard Beschow
Am 22. April 2023 19:21:12 UTC schrieb BALATON Zoltan : >On Sat, 22 Apr 2023, Bernhard Beschow wrote: >> Am 22. April 2023 17:23:56 UTC schrieb BALATON Zoltan : >>> On Sat, 22 Apr 2023, Bernhard Beschow wrote: The VIA south bridge allows the legacy IDE interrupts to be routed to four d

Re: [PATCH 02/13] hw/ide/via: Implement ISA IRQ routing

2023-04-22 Thread BALATON Zoltan
On Sat, 22 Apr 2023, Bernhard Beschow wrote: Am 22. April 2023 17:23:56 UTC schrieb BALATON Zoltan : On Sat, 22 Apr 2023, Bernhard Beschow wrote: The VIA south bridge allows the legacy IDE interrupts to be routed to four different ISA interrupts. This can be configured through the 0x4a register

Re: [PATCH 02/13] hw/ide/via: Implement ISA IRQ routing

2023-04-22 Thread Bernhard Beschow
Am 22. April 2023 17:23:56 UTC schrieb BALATON Zoltan : >On Sat, 22 Apr 2023, Bernhard Beschow wrote: >> The VIA south bridge allows the legacy IDE interrupts to be routed to four >> different ISA interrupts. This can be configured through the 0x4a register in >> the PCI configuration space of t

Re: [PATCH 02/13] hw/ide/via: Implement ISA IRQ routing

2023-04-22 Thread BALATON Zoltan
On Sat, 22 Apr 2023, Bernhard Beschow wrote: The VIA south bridge allows the legacy IDE interrupts to be routed to four different ISA interrupts. This can be configured through the 0x4a register in the PCI configuration space of the ISA function. The default routing matches the legacy ISA IRQs, t

[PATCH 02/13] hw/ide/via: Implement ISA IRQ routing

2023-04-22 Thread Bernhard Beschow
The VIA south bridge allows the legacy IDE interrupts to be routed to four different ISA interrupts. This can be configured through the 0x4a register in the PCI configuration space of the ISA function. The default routing matches the legacy ISA IRQs, that is 14 and 15. Implement this missing piece