[PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode

From: Ian Brockbank The interrupt-level threshold (xintthresh) CSR holds an 8-bit field for the threshold level of the associated privilege mode. For horizontal interrupts, only the ones with higher interrupt levels than the threshold level are allowed to preempt. Signed-off-by: Ian Brockbank

Re: [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode

Frank Chang 於 2021年6月27日 週日 上午1:23寫道： > LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道： > >> The interrupt-level threshold (xintthresh) CSR holds an 8-bit field >> for the threshold level of the associated privilege mode. >> >> For horizontal interrupts, only the ones with higher interrupt levels >> than th

Re: [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道： > The interrupt-level threshold (xintthresh) CSR holds an 8-bit field > for the threshold level of the associated privilege mode. > > For horizontal interrupts, only the ones with higher interrupt levels > than the threshold level are allowed to preempt. > > Si

[RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode

The interrupt-level threshold (xintthresh) CSR holds an 8-bit field for the threshold level of the associated privilege mode. For horizontal interrupts, only the ones with higher interrupt levels than the threshold level are allowed to preempt. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h