On 8/20/21 3:40 PM, Greg Kurz wrote:
> On Mon, 9 Aug 2021 15:45:22 +0200
> Cédric Le Goater wrote:
>
>> The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have
>> HAIL but since it does not break the modeling and that we don't plan
>> to support DD1, modify the LPCR mask of all the POW
On Mon, 9 Aug 2021 15:45:22 +0200
Cédric Le Goater wrote:
> The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have
> HAIL but since it does not break the modeling and that we don't plan
> to support DD1, modify the LPCR mask of all the POWER10 family.
>
Maybe consider dropping DD1 a
The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have
HAIL but since it does not break the modeling and that we don't plan
to support DD1, modify the LPCR mask of all the POWER10 family.
Setting the HAIL bit is a requirement to support the scv instruction
on PowerNV POWER10 platforms