Re: [PATCH 01/13] target/riscv: Sign extend pc for different ol

2021-11-01 Thread Richard Henderson
On 11/1/21 6:01 AM, LIU Zhiwei wrote: +static void gen_set_pc(DisasContext *ctx, target_ulong dest) +{ +TCGv t = tcg_constant_tl(dest); +switch (get_ol(ctx)) { +case MXL_RV32: +tcg_gen_ext32s_tl(cpu_pc, t); Don't compute with tcg to do what you can in C. Dest is constant. A

[PATCH 01/13] target/riscv: Sign extend pc for different ol

2021-11-01 Thread LIU Zhiwei
When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei --- target/riscv/translate.c | 23 +++ 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d57bc97b5..7d7