Re: [PATCH 01/12] target/riscv: Source vector registers cannot overlap mask register

Reviewed-by: Max Chou On 2025/1/26 3:20 PM, Anton Blanchard wrote: Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++---

[PATCH 01/12] target/riscv: Source vector registers cannot overlap mask register

Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/target/ris