On 8/30/21 3:00 PM, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 8/30/21 8:24 AM, Richard Henderson wrote:
Currently, we have support for optimizing redundant zero extensions,
which I think was done with x86 and aarch64 in mind, which zero-extend
all 32-bit operations into the 64-bit register.
Hi Richard,
On 8/30/21 8:24 AM, Richard Henderson wrote:
> Currently, we have support for optimizing redundant zero extensions,
> which I think was done with x86 and aarch64 in mind, which zero-extend
> all 32-bit operations into the 64-bit register.
>
> But targets like Alpha, MIPS, and RISC-V d
Currently, we have support for optimizing redundant zero extensions,
which I think was done with x86 and aarch64 in mind, which zero-extend
all 32-bit operations into the 64-bit register.
But targets like Alpha, MIPS, and RISC-V do sign-extensions instead.
The last 5 patches address this.
But bef
