On 5/12/24 18:08, Sven Schnelle wrote:
Philippe Mathieu-Daudé writes:
Cc'ing Helge & Sven as I'm going to skip this series.
Suggestion:
-- >8 --
diff --git a/MAINTAINERS b/MAINTAINERS
index 1b79767d61..be7535b55e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -254,6 +254,8 @@ F: target/hexago
Philippe Mathieu-Daudé writes:
> Cc'ing Helge & Sven as I'm going to skip this series.
>
> Suggestion:
>
> -- >8 --
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1b79767d61..be7535b55e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -254,6 +254,8 @@ F: target/hexagon/gen_idef_parser_funcs.
Cc'ing Helge & Sven as I'm going to skip this series.
Suggestion:
-- >8 --
diff --git a/MAINTAINERS b/MAINTAINERS
index 1b79767d61..be7535b55e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -254,6 +254,8 @@ F: target/hexagon/gen_idef_parser_funcs.py
HPPA (PA-RISC) TCG CPUs
M: Richard Henderson
Most of the patches lead up to implementing CF_PCREL.
Along the way there is a grab bag of code updates (TCG_COND_TST*),
bug fixes (space changes during branch-in-branch-delay-slot),
and implementation of features (PSW bits B, X, T, H, L).
Sven reported that PSW L tripped up HP/UX, so possibly the
