On Sat, Nov 30, 2024 at 12:44 AM Philippe Mathieu-Daudé
wrote:
>
> The HTIF interface is RISC-V specific, add
> it within the MAINTAINERS section covering
> hw/riscv/.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> IMHO 'RISC-V TCG CPUs' should cover
On 11/29/24 12:43 PM, Philippe Mathieu-Daudé wrote:
The HTIF interface is RISC-V specific, add
it within the MAINTAINERS section covering
hw/riscv/.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Daniel Henrique Barboza
IMHO 'RISC-V TCG CPUs' should cover target/riscv/ which are
The HTIF interface is RISC-V specific, add
it within the MAINTAINERS section covering
hw/riscv/.
Signed-off-by: Philippe Mathieu-Daudé
---
IMHO 'RISC-V TCG CPUs' should cover target/riscv/ which are
the accelerator-facing implementations, and each machine or
device in hw/riscv/ should have its ow
