Re: [PATCH] target/riscv: fix right shifts shamt value for rv128c

Le 09/07/2022 à 10:52, Weiwei Li a écrit : 在 2022/7/8 下午11:00, Frédéric Pétrot 写道: For rv128c right shifts, the 6-bit shamt is sign extended to 7 bits. Signed-off-by: Frédéric Pétrot --- target/riscv/insn16.decode | 7 --- disas/riscv.c | 27 +-- t

Re: [PATCH] target/riscv: fix right shifts shamt value for rv128c

在 2022/7/8 下午11:00, Frédéric Pétrot 写道: For rv128c right shifts, the 6-bit shamt is sign extended to 7 bits. Signed-off-by: Frédéric Pétrot --- target/riscv/insn16.decode | 7 --- disas/riscv.c | 27 +-- target/riscv/translate.c | 12 +++-

[PATCH] target/riscv: fix right shifts shamt value for rv128c

For rv128c right shifts, the 6-bit shamt is sign extended to 7 bits. Signed-off-by: Frédéric Pétrot --- target/riscv/insn16.decode | 7 --- disas/riscv.c | 27 +-- target/riscv/translate.c | 12 +++- 3 files changed, 36 insertions(+), 10 deleti