Re: [PATCH] target/riscv: Fix shift count overflow

On 2/24/24 10:02, demin.han wrote: The result of (8 - 3 - vlmul) is negtive when vlmul >= 6, and results in wrong vill. Signed-off-by: demin.han --- target/riscv/vector_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/ris

[PATCH] target/riscv: Fix shift count overflow

The result of (8 - 3 - vlmul) is negtive when vlmul >= 6, and results in wrong vill. Signed-off-by: demin.han --- target/riscv/vector_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 84cec73eb2..ced0a