On Thu, Oct 20, 2022 at 7:29 AM Leon Schuermann
wrote:
>
> Alistair Francis writes:
> >> @@ -310,10 +311,17 @@ bool pmp_hart_has_privs(CPURISCVState *env,
> >> target_ulong addr,
> >> }
> >>
> >> if (size == 0) {
> >> -if (riscv_feature(env, RISCV_FEATURE_MMU)) {
> >> +
Alistair Francis writes:
>> @@ -310,10 +311,17 @@ bool pmp_hart_has_privs(CPURISCVState *env,
>> target_ulong addr,
>> }
>>
>> if (size == 0) {
>> -if (riscv_feature(env, RISCV_FEATURE_MMU)) {
>> +if (riscv_cpu_mxl(env) == MXL_RV32) {
>> +satp_mode = SATP32_M
On Sat, Sep 10, 2022 at 1:24 AM wrote:
>
> From: Leon Schuermann
>
> This commit fixes PMP address access checks with non page-aligned PMP
> regions on harts with MPU enabled. Without this change, the presence
> of an MPU in the virtual CPU model would influence the PMP address
> check behavior w
From: Leon Schuermann
This commit fixes PMP address access checks with non page-aligned PMP
regions on harts with MPU enabled. Without this change, the presence
of an MPU in the virtual CPU model would influence the PMP address
check behavior when an access size was unknown (`size == 0`),
regardl
