On 6/22/22 16:32, Víctor Colombo wrote:
FPSCR_* bit values in QEMU are in the 'inverted' order from what Power
ISA defines (e.g. FPSCR.FI is bit 46 but is defined as 17 in cpu.h).
Now that PPC_BIT_NR macro was introduced to fix this situation for the
MSR bits, we can use it for the FPSCR bits
Víctor Colombo writes:
> FPSCR_* bit values in QEMU are in the 'inverted' order from what Power
> ISA defines (e.g. FPSCR.FI is bit 46 but is defined as 17 in cpu.h).
> Now that PPC_BIT_NR macro was introduced to fix this situation for the
> MSR bits, we can use it for the FPSCR bits too.
>
> Als
FPSCR_* bit values in QEMU are in the 'inverted' order from what Power
ISA defines (e.g. FPSCR.FI is bit 46 but is defined as 17 in cpu.h).
Now that PPC_BIT_NR macro was introduced to fix this situation for the
MSR bits, we can use it for the FPSCR bits too.
Also, adjust the comments to make then
