Hi David,
On Wed, Feb 10, 2021 at 10:09 AM David Gibson
wrote:
>
> On Wed, Feb 10, 2021 at 09:53:53AM +0800, Bin Meng wrote:
> > Hi David,
> >
> > On Wed, Feb 10, 2021 at 9:50 AM David Gibson
> > wrote:
> > >
> > > On Mon, Feb 08, 2021 at 05:40:58PM +0800, Bin Meng wrote:
> > > > From: Bin Meng
On Wed, Feb 10, 2021 at 09:53:53AM +0800, Bin Meng wrote:
> Hi David,
>
> On Wed, Feb 10, 2021 at 9:50 AM David Gibson
> wrote:
> >
> > On Mon, Feb 08, 2021 at 05:40:58PM +0800, Bin Meng wrote:
> > > From: Bin Meng
> > >
> > > There are several bits in L2CSR0 (exists in the e500mc/e5500/e6500
>
Hi David,
On Wed, Feb 10, 2021 at 9:50 AM David Gibson
wrote:
>
> On Mon, Feb 08, 2021 at 05:40:58PM +0800, Bin Meng wrote:
> > From: Bin Meng
> >
> > There are several bits in L2CSR0 (exists in the e500mc/e5500/e6500
> > core) that should be self-cleared when written:
> >
> > - L2FI (L2 cache
On Mon, Feb 08, 2021 at 05:40:58PM +0800, Bin Meng wrote:
> From: Bin Meng
>
> There are several bits in L2CSR0 (exists in the e500mc/e5500/e6500
> core) that should be self-cleared when written:
>
> - L2FI (L2 cache flash invalidate)
> - L2FL (L2 cache flush)
> - L2LFC (L2 cache lock flash cl
From: Bin Meng
There are several bits in L2CSR0 (exists in the e500mc/e5500/e6500
core) that should be self-cleared when written:
- L2FI (L2 cache flash invalidate)
- L2FL (L2 cache flush)
- L2LFC (L2 cache lock flash clear)
Add a write helper to emulate this behavior.
Signed-off-by: Bin Men
