Re: [PATCH] target/i386: correctly mask SSE4a bit indices in register operands

2022-09-19 Thread Richard Henderson
On 9/18/22 09:18, Paolo Bonzini wrote: SSE4a instructions EXTRQ and INSERTQ have two bit index operands, that can be immediates or taken from an XMM register. In both cases, the fields are 6-bit wide and the top two bits in the byte are ignored. translate.c is doing that correctly for the immed

[PATCH] target/i386: correctly mask SSE4a bit indices in register operands

2022-09-18 Thread Paolo Bonzini
SSE4a instructions EXTRQ and INSERTQ have two bit index operands, that can be immediates or taken from an XMM register. In both cases, the fields are 6-bit wide and the top two bits in the byte are ignored. translate.c is doing that correctly for the immediate case, but not for the XMM case, so f