On Mon, 21 Nov 2022 at 15:08, Timofey Kutergin wrote:
>
> cortex-a55 is one of newer armv8.2+ CPUs supporting native
> Privileged Access Never (PAN) feature. Using this CPU
> provides access to this feature without using fictitious "max"
> CPU.
>
> Signed-off-by: Timofey Kutergin
Thanks;
cortex-a55 is one of newer armv8.2+ CPUs supporting native
Privileged Access Never (PAN) feature. Using this CPU
provides access to this feature without using fictitious "max"
CPU.
Signed-off-by: Timofey Kutergin
---
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c| 1 +
targe
Thank you very much for your comments, I have tried to fix them.
Regarding L3 cache - cortex-a55 may have or not have it. CLIDR register
value shows that this specific instance (dumped from odroid c4) does not
have it.
But if you think that having L3 cache may be useful - it may be added too...
BR
Hi all,
added some references to TRM but honestly many fields were dumped from
hardware - odroid c4/amlogic s905x3/quad cortex-a55
On Thu, Nov 17, 2022 at 6:03 PM Daniel Baluta wrote:
> Patch looks good to me.
>
> Maybe you might add some references to chapters from RM where this numbers
>
> co
On Thu, 10 Nov 2022 at 09:04, Timofey Kutergin wrote:
>
> cortex-a55 is one of newer armv8.2+ CPUs supporting native
> Privileged Access Never (PAN) feature.
Hi; thanks for this patch. There are a few missing ID register
values below, but otherwise it looks good.
> Using this CPU
> provide
Patch looks good to me.
Maybe you might add some references to chapters from RM where this numbers
come from. Similar with aarch64_a76_initfn function for example.
cortex-a55 is one of newer armv8.2+ CPUs supporting native
Privileged Access Never (PAN) feature. Using this CPU
provides access to this feature without using fictious "max"
CPU.
Signed-off-by: Timofey Kutergin
---
hw/arm/virt.c | 1 +
target/arm/cpu64.c | 55 ++
