On Tue, 4 Aug 2020 at 21:38, Richard Henderson
wrote:
>
> On 8/3/20 9:54 AM, Peter Maydell wrote:
> > +case 14:
> > +switch (mode) {
> > +case ARM_CPU_MODE_USR:
> > +case ARM_CPU_MODE_SYS:
> > +return 14;
> > +case ARM_CPU_MODE_HYP:
> > +
On 8/3/20 9:54 AM, Peter Maydell wrote:
> +case 14:
> +switch (mode) {
> +case ARM_CPU_MODE_USR:
> +case ARM_CPU_MODE_SYS:
> +return 14;
> +case ARM_CPU_MODE_HYP:
> +return 16;
Hyp uses LR_usr...
> +case ARM_CPU_MODE_IRQ:
> +
When a coprocessor instruction in an AArch32 guest traps to AArch32
Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields
which are simply copies of the Rt and Rt2 fields from the trapped
instruction. However, if the instruction is trapped from AArch32 to
an AArch64 higher exception le
