On Thu, 28 Apr 2022 at 16:19, Richard Henderson
wrote:
>
> On 4/28/22 05:56, Peter Maydell wrote:
> > On Wed, 27 Apr 2022 at 05:23, Richard Henderson
> > wrote:
> >>
> >> This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
> >> (indirect branch from register other than x16/x17).
On 4/28/22 05:56, Peter Maydell wrote:
On Wed, 27 Apr 2022 at 05:23, Richard Henderson
wrote:
This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
(indirect branch from register other than x16/x17). The linux kernel
sets this in bti_enable().
Resolves: https://gitlab.com/qemu
On Wed, 27 Apr 2022 at 05:23, Richard Henderson
wrote:
>
> This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
> (indirect branch from register other than x16/x17). The linux kernel
> sets this in bti_enable().
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
> Sig
This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
(indirect branch from register other than x16/x17). The linux kernel
sets this in bti_enable().
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998
Signed-off-by: Richard Henderson
---
target/arm/cpu.c
