On Thu, 21 Nov 2024 at 17:16, Michael Tokarev wrote:
>
> According to Cortex-R5 r1p2 manual, register with opcode2=0 is
> BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
> qemu labels them. Just swap the labels to avoid confusion, -
> both registers are implemented as always-zero
On 11/21/24 11:16, Michael Tokarev wrote:
According to Cortex-R5 r1p2 manual, register with opcode2=0 is
BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
qemu labels them. Just swap the labels to avoid confusion, -
both registers are implemented as always-zero.
Signed-off-by: Mi
According to Cortex-R5 r1p2 manual, register with opcode2=0 is
BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
qemu labels them. Just swap the labels to avoid confusion, -
both registers are implemented as always-zero.
Signed-off-by: Michael Tokarev
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target/arm/tcg/cpu32.c |
