Re: [PATCH] riscv: Fix bug in setting xPIE of CSR for MRET and SRET instructions

2020-01-21 Thread Ian Jiang
Just find that there is a previous patch at https://github.com/palmer-dabbelt/qemu/commit/a37f21c27d3e2342c2080aafd4cfe7e949612428 -- Ian Jiang Alistair Francis 于2020年1月21日周二 下午6:48写道： > > On Tue, Jan 21, 2020 at 8:08 PM Ian Jiang wrote: > > > > According to the RISC-V specification, when execut

Re: [PATCH] riscv: Fix bug in setting xPIE of CSR for MRET and SRET instructions

2020-01-21 Thread Alistair Francis
On Tue, Jan 21, 2020 at 8:08 PM Ian Jiang wrote: > > According to the RISC-V specification, when executing an MRET or SRET > instruction, xPIE in mstatus or sstatus should be set to 1. The orginal > QEMU does not give the right operations. > This patch fix the problem. > > Signed-off-by: Ian Jiang

[PATCH] riscv: Fix bug in setting xPIE of CSR for MRET and SRET instructions

2020-01-21 Thread Ian Jiang
According to the RISC-V specification, when executing an MRET or SRET instruction, xPIE in mstatus or sstatus should be set to 1. The orginal QEMU does not give the right operations. This patch fix the problem. Signed-off-by: Ian Jiang --- target/riscv/op_helper.c | 4 ++-- 1 file changed, 2 ins