re-examining the PCI spec (3.2.2.3.2) and QEMU's PCI host bridge
implementations, I agree .min_access_size = 4 is actually more correct
I'll update the patch(v4) to:
-Set .min_access_size = 4 in MemoryRegionOps
-Remove the now-unnecessary bswap16 handling
On Mon, Mar 31, 2025 at 5:04 PM Philippe
On 29/3/25 12:30, Rakesh J wrote:
Thanks for feedback on [PATCH v1]!
I've posted v2 incorporating the suggestions:ve posted v2 incorporating
your suggestions
Paolo: You pointed out the size issue with .min_access_size = 1
and .max_access_size = 4, where bswap32 was wrong for 2-byte accesse
On Sat, Mar 29, 2025 at 12:31 PM Rakesh J wrote:
> Paolo: You pointed out the size issue with .min_access_size = 1 and
> .max_access_size = 4, where bswap32 was wrong for 2-byte accesses. I’ve fixed
> this with size-appropriate swaps (bswap16 for 2-byte, bswap32 for 4-byte). On
> the extra swa
Thanks for feedback on [PATCH v1]!
I've posted v2 incorporating the suggestions:ve posted v2 incorporating
your suggestions
Paolo: You pointed out the size issue with .min_access_size = 1 and
.max_access_size = 4, where bswap32 was wrong for 2-byte accesses. I’ve
fixed this with size-appropriate
On 28/3/25 18:34, Paolo Bonzini wrote:
On Fri, Mar 28, 2025 at 3:16 PM BALATON Zoltan wrote:
It should be fine. You should take into account:
- the endianness produced by pci_data_read/pci_data_write (always little
endian)
- the endianness expected by the guest (big endian under the conditio
On 28/03/2025 15.16, BALATON Zoltan wrote:
On Fri, 28 Mar 2025, Paolo Bonzini wrote:
On 3/27/25 21:50, BALATON Zoltan wrote:
On Thu, 27 Mar 2025, rakeshj wrote:
The GT-64120 PCI controller requires special handling where:
1. Host bridge (device 0) must use native endianness
2. Other devices fo
On Fri, Mar 28, 2025 at 3:16 PM BALATON Zoltan wrote:
> > It should be fine. You should take into account:
> >
> > - the endianness produced by pci_data_read/pci_data_write (always little
> > endian)
> >
> > - the endianness expected by the guest (big endian under the conditions in
> > the patch)
On Fri, 28 Mar 2025, Paolo Bonzini wrote:
On 3/27/25 21:50, BALATON Zoltan wrote:
On Thu, 27 Mar 2025, rakeshj wrote:
The GT-64120 PCI controller requires special handling where:
1. Host bridge (device 0) must use native endianness
2. Other devices follow MByteSwap bit in GT_PCI0_CMD
Previous
On 3/27/25 21:50, BALATON Zoltan wrote:
On Thu, 27 Mar 2025, rakeshj wrote:
The GT-64120 PCI controller requires special handling where:
1. Host bridge (device 0) must use native endianness
2. Other devices follow MByteSwap bit in GT_PCI0_CMD
Previous implementation accidentally swapped all acc
On Thu, 27 Mar 2025, rakeshj wrote:
The GT-64120 PCI controller requires special handling where:
1. Host bridge (device 0) must use native endianness
2. Other devices follow MByteSwap bit in GT_PCI0_CMD
Previous implementation accidentally swapped all accesses, breaking
host bridge detection (ls
The GT-64120 PCI controller requires special handling where:
1. Host bridge (device 0) must use native endianness
2. Other devices follow MByteSwap bit in GT_PCI0_CMD
Previous implementation accidentally swapped all accesses, breaking
host bridge detection (lspci -d 11ab:4620). This fix:
- Adds d
11 matches
Mail list logo
