On Fri, Jun 07, 2024 at 03:29:33PM -0700, Joel Holdsworth via wrote:
> In the existing design, TTCR is prone to undercounting when running in
> continuous mode. This manifests as a timer interrupt appearing to
> trigger a few cycles prior to the deadline set in SPR_TTMR_TP.
>
> When the timer trig
On Mon, Jun 10, 2024 at 07:29:15PM +, Joel Holdsworth wrote:
> Hi Stafford, thanks for your response.
>
> > - You sent this 2 times, is the only change in v2 the sender address?
>
> Yes, I was just having some difficulty with Git and SMTP. Should be fixed now.
OK.
> >> In the existing desig
Hi Stafford, thanks for your response.
> - You sent this 2 times, is the only change in v2 the sender address?
Yes, I was just having some difficulty with Git and SMTP. Should be fixed now.
>> In the existing design, TTCR is prone to undercounting when running in
>> continuous mode. This manife
Hi Joel,
I am away and wont be able to have too much time to look at this.
But have a few comments below and questions.
- You sent this 2 times, is the only change in v2 the sender address?
On Fri, Jun 07, 2024 at 03:29:33PM -0700, Joel Holdsworth via wrote:
> In the existing design, TTCR is p
In the existing design, TTCR is prone to undercounting when running in
continuous mode. This manifests as a timer interrupt appearing to
trigger a few cycles prior to the deadline set in SPR_TTMR_TP.
When the timer triggers, the virtual time delta in nanoseconds between
the time when the timer was
