Re: [QEMU-SECURITY] [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register

2021-02-03 Thread P J P
On Tuesday, 2 February, 2021, 08:45:19 pm IST, Peter Maydell wrote:  >On the CVE: > >Since this can affect systems using KVM, this is a security bug for >us. However, it only affects an uncommon configuration: >you are only vulnerable if you are using "kernel-irqchip=off" >(the default is 'on', a

Re: [QEMU-SECURITY] [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register

2021-02-02 Thread Alexander Bulekov
On 210202 1221, Peter Maydell wrote: > On Tue, 2 Feb 2021 at 09:32, Philippe Mathieu-Daudé wrote: > > > > On 2/2/21 7:21 AM, P J P wrote: > > > On Sunday, 31 January, 2021, 08:48:26 pm IST, Philippe Mathieu-Daudé > > > wrote: > > >> Forwarding to qemu-security@ to see if this issue is worth a CV

Re: [QEMU-SECURITY] [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register

2021-02-02 Thread Peter Maydell
On Tue, 2 Feb 2021 at 09:32, Philippe Mathieu-Daudé wrote: > > On 2/2/21 7:21 AM, P J P wrote: > > On Sunday, 31 January, 2021, 08:48:26 pm IST, Philippe Mathieu-Daudé > > wrote: > >> Forwarding to qemu-security@ to see if this issue is worth a CVE. > >> > >> | On 1/31/21 11:34 AM, Philippe Math

Re: [QEMU-SECURITY] [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register

2021-02-02 Thread Philippe Mathieu-Daudé
On 2/2/21 7:21 AM, P J P wrote: > On Sunday, 31 January, 2021, 08:48:26 pm IST, Philippe Mathieu-Daudé > wrote:  >> Forwarding to qemu-security@ to see if this issue is worth a CVE. >> >> | On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote: >> | > Per the ARM Generic Interrupt Controller Architec

Re: [QEMU-SECURITY] [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register

2021-02-01 Thread P J P
On Sunday, 31 January, 2021, 08:48:26 pm IST, Philippe Mathieu-Daudé wrote:  >Forwarding to qemu-security@ to see if this issue is worth a CVE. > > | On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote: > | > Per the ARM Generic Interrupt Controller Architecture specification > | > (document "ARM I

Re: [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register

2021-01-31 Thread Philippe Mathieu-Daudé
Forwarding to qemu-security@ to see if this issue is worth a CVE. On 1/31/21 12:57 PM, P J P wrote: > +-- On Sun, 31 Jan 2021, Philippe Mathieu-Daudé wrote --+ > | On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote: > | > Per the ARM Generic Interrupt Controller Architecture specification > | > (do

Re: [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register

2021-01-31 Thread P J P
+-- On Sun, 31 Jan 2021, Philippe Mathieu-Daudé wrote --+ | On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote: | > Per the ARM Generic Interrupt Controller Architecture specification | > (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit, | > not 10: | > | > - Table 4-21 GICD

Re: [PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register

2021-01-31 Thread Philippe Mathieu-Daudé
On 1/31/21 11:34 AM, Philippe Mathieu-Daudé wrote: > Per the ARM Generic Interrupt Controller Architecture specification > (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit, > not 10: > > - 4.3 Distributor register descriptions > - 4.3.15 Software Generated Interrupt Registe

[PATCH] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register

2021-01-31 Thread Philippe Mathieu-Daudé
Per the ARM Generic Interrupt Controller Architecture specification (document "ARM IHI 0048B.b (ID072613)"), the SGIINTID field is 4 bit, not 10: - 4.3 Distributor register descriptions - 4.3.15 Software Generated Interrupt Register, GICD_SG - Table 4-21 GICD_SGIR bit assignments The