Richard Henderson writes:
> On 12/13/21 1:02 PM, Alex Bennée wrote:
>>> +cpu->midr = 0x410fc0f1;
>> hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f)
>> but
>> I can't find the actual value in the TRM.
>
> https://developer.arm.com/documentation/ddi0434/c
>
> has exactly t
The goal for me was to eventually add the SAMA5D, so I might have made some
assumptions that were not correct for all devices. My apologies for the
typos.
I will add those changes and re-submit.
On Mon, Dec 13, 2021 at 3:46 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 12/13/21
On 12/13/21 1:02 PM, Alex Bennée wrote:
+cpu->midr = 0x410fc0f1;
hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f) but
I can't find the actual value in the TRM.
https://developer.arm.com/documentation/ddi0434/c
has exactly this value at the top of table 4-9.
+cpu-
Byron Lathi writes:
> Add support for the Cortex-A5. These changes are based off of the A7 and
> A9 init functions, using the appropriate values from the technical
> reference manual for the A5.
>
> Signed-off-by: Byron Lathi
> ---
> target/arm/cpu_tcg.c | 37 +
On 12/13/21 10:24 AM, Byron Lathi wrote:
Add support for the Cortex-A5. These changes are based off of the A7 and
A9 init functions, using the appropriate values from the technical
reference manual for the A5.
Signed-off-by: Byron Lathi
---
target/arm/cpu_tcg.c | 37 ++
On 12/13/21 19:24, Byron Lathi wrote:
> Add support for the Cortex-A5. These changes are based off of the A7 and
> A9 init functions, using the appropriate values from the technical
> reference manual for the A5.
>
> Signed-off-by: Byron Lathi
> ---
> target/arm/cpu_tcg.c | 37 ++
Add support for the Cortex-A5. These changes are based off of the A7 and
A9 init functions, using the appropriate values from the technical
reference manual for the A5.
Signed-off-by: Byron Lathi
---
target/arm/cpu_tcg.c | 37 +
1 file changed, 37 insertions(+
