Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable

On Thu, Nov 4, 2021 at 4:47 AM Bin Meng wrote: > > On Tue, Oct 26, 2021 at 4:41 AM Atish Patra wrote: > > > > The RISC-V privilege specification provides flexibility to implement > > any number of counters from 29 programmable counters. However, the QEMU > > implements all the counters. > > > > M

Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable

On Tue, Oct 26, 2021 at 4:41 AM Atish Patra wrote: > > The RISC-V privilege specification provides flexibility to implement > any number of counters from 29 programmable counters. However, the QEMU > implements all the counters. > > Make it configurable through pmu config parameter which now will

Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable

On Tue, Oct 26, 2021 at 6:41 AM Atish Patra wrote: > > The RISC-V privilege specification provides flexibility to implement > any number of counters from 29 programmable counters. However, the QEMU > implements all the counters. > > Make it configurable through pmu config parameter which now will

[ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable

The RISC-V privilege specification provides flexibility to implement any number of counters from 29 programmable counters. However, the QEMU implements all the counters. Make it configurable through pmu config parameter which now will indicate how many programmable counters should be implemented b