[PATCH 0/2] support BLKSECDISCARD

2021-11-14 Thread yadong . qi
From: Yadong Qi Support BLKSECDISCARD passthrough for raw host_device backend. For virtio-blk device: Add new virtio feature: VIRTIO_BLK_F_SECDISCARD. Add new virtio command: VIRTIO_BLK_T_SECDISCARD. Usage: qemu-system-x86_64 \ ... \ -drive file=/dev/mmcblk0p2,if=none

[PATCH 2/2] virtio-blk: support BLKSECDISCARD

2021-11-14 Thread yadong . qi
From: Yadong Qi Add new virtio feature: VIRTIO_BLK_F_SECDISCARD. Add new virtio command: VIRTIO_BLK_T_SECDISCARD. This feature is disabled by default, it will check the backend bs->open_flags & BDRV_O_SECDISCARD, enable it if BDRV_O_SECDISCARD is supported. Signed-off-by: Yadong Qi

[PATCH 1/2] block:hdev: support BLKSECDISCARD

2021-11-14 Thread yadong . qi
From: Yadong Qi Add a new option "secdiscard" for block drive. Parse it and record it in bs->open_flags as bit(BDRV_O_SECDISCARD). Add a new BDRV_REQ_SECDISCARD bit for secure discard request from virtual device. For host_device backend: implement by ioctl(BLKSECDISCARD) on re

[PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking

2019-11-24 Thread yadong . qi
From: "Qi, Yadong" The following patches are to refine/fix issues of reserved fields checking logic of Second-Level Paging Entries of VT-d: - split the resevred fields arrays into two ones, - large page only effect for L2(2M) and L3(1G), so remove checking of L1 and L4 for large page, - when dt

[PATCH v3 1/2] intel_iommu: refine SL-PEs reserved fields checking

2019-11-24 Thread yadong . qi
From: "Qi, Yadong" 1. split the resevred fields arrays into two ones, 2. large page only effect for L2(2M) and L3(1G), so remove checking of L1 and L4 for large page. Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 37 ++--

[PATCH v3 2/2] intel_iommu: TM field should not be in reserved bits

2019-11-24 Thread yadong . qi
From: "Qi, Yadong" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 9 ++--- hw/i386/intel_iommu_internal.h | 13 ++--- 2 files changed, 16 insertions(+), 6 de

[PATCH v3 0/2] Refine Second-Level Paging Entries reserved fields checking

2019-11-24 Thread yadong . qi
From: "Qi, Yadong" The following patches are to refine/fix issues of reserved fields checking logic of Second-Level Paging Entries of VT-d: - split the resevred fields arrays into two ones, - large page only effect for L2(2M) and L3(1G), so remove checking of L1 and L4 for large page, - when dt