Re: Holding RISCV CPUs in reset

Thanks for the info Peter. I will look into the ARM implementation. Cheers, Vy On Tue, 15 Feb 2022, 4:49 pm Peter Maydell, wrote: > On Tue, 15 Feb 2022 at 10:30, vysakh pillai > wrote: > > > > Hi, > > In an SMP system like the sifive_u machine which has a RISCV e_cpu

Holding RISCV CPUs in reset

Hi, In an SMP system like the sifive_u machine which has a RISCV e_cpu as hart0 and a set of u_cpus as hart 1-N, is there a way to start just the hart0 and hold the other CPUs in reset until explicitly released by hart0 SW? I am working on a machine similar to the sifive_u machine that has a se