[PATCH v6 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs

From: Tobias Röhmel RVBAR shadows RVBAR_ELx where x is the highest exception level if the highest EL is not EL3. This patch also allows ARMv8 CPUs to change the reset address with the rvbar property. Signed-off-by: Tobias Röhmel Reviewed-by: Peter Maydell --- target/arm/cpu.c| 6 +-

[PATCH v6 3/7] target/arm: Make stage_2_format for cache attributes optional

From: Tobias Röhmel The v8R PMSAv8 has a two-stage MPU translation process, but, unlike VMSAv8, the stage 2 attributes are in the same format as the stage 1 attributes (8-bit MAIR format). Rather than converting the MAIR format to the format used for VMSA stage 2 (bits [5:2] of a VMSA stage 2 des

[PATCH v6 1/7] target/arm: Don't add all MIDR aliases for cores that implement PMSA

From: Tobias Röhmel Cores with PMSA have the MPUIR register which has the same encoding as the MIDR alias with opc2=4. So we only add that alias if we are not realizing a core that implements PMSA. Signed-off-by: Tobias Röhmel Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- tar

[PATCH v6 6/7] target/arm: Add PMSAv8r functionality

From: Tobias Röhmel Add PMSAv8r translation. Signed-off-by: Tobias Röhmel Reviewed-by: Peter Maydell --- target/arm/ptw.c | 126 ++- 1 file changed, 104 insertions(+), 22 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7d1982970

[PATCH v6 5/7] target/arm: Add PMSAv8r registers

From: Tobias Röhmel Signed-off-by: Tobias Röhmel --- target/arm/cpu.c | 28 +++- target/arm/cpu.h | 6 + target/arm/helper.c | 302 +++ target/arm/machine.c | 28 4 files changed, 360 insertions(+), 4 deletions(-) diff --git a/target/ar

[PATCH v6 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32

From: Tobias Röhmel ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias Röhmel Reviewed-by: P

[PATCH v6 7/7] target/arm: Add ARM Cortex-R52 CPU

From: Tobias Röhmel All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 Signed-off-by: Tobias Röhmel Reviewed-by: Peter Maydell --- target/arm/cpu_tcg.c | 42 ++ 1 file changed, 42 insertions(+) diff --git a/target/arm/cpu_tcg.

[PATCH v6 0/7] Add ARM Cortex-R52 CPU

From: Tobias Röhmel Sorry for the "Reviewed-by" messup. I missed that on the explanation page. Thanks again for the review :) v6: patch 5: - I also changed HPRENR from ARM_CP_ALIAS to ARM_CP_NO_RAW. Its state is also present in the HPRLAR registers, but it doesn't make sense to access it raw

[PATCH v5 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32

From: Tobias Röhmel ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias Röhmel --- target/ar

[PATCH v5 5/7] target/arm: Add PMSAv8r registers

From: Tobias Röhmel Signed-off-by: Tobias Röhmel --- target/arm/cpu.c | 24 +++- target/arm/cpu.h | 6 + target/arm/helper.c | 299 +++ target/arm/machine.c | 28 4 files changed, 356 insertions(+), 1 deletion(-) diff --git a/target/arm

[PATCH v5 3/7] target/arm: Make stage_2_format for cache attributes optional

From: Tobias Röhmel The v8R PMSAv8 has a two-stage MPU translation process, but, unlike VMSAv8, the stage 2 attributes are in the same format as the stage 1 attributes (8-bit MAIR format). Rather than converting the MAIR format to the format used for VMSA stage 2 (bits [5:2] of a VMSA stage 2 des

[PATCH v5 0/7] Add ARM Cortex-R52 CPU

From: Tobias Röhmel No worries about the delay. I'm glad you are looking at it :) v5: 1. Adjusted the spacing as requested 2. Removed cp 15 3. Rebased and put assert back 4. Fixed indention issues 5. - Made hprbar etc pointers instead of arrays - Fixed the logic/bound issues - For the VMSTATE ch

[PATCH v5 1/7] target/arm: Don't add all MIDR aliases for cores that implement PMSA

From: Tobias Röhmel Cores with PMSA have the MPUIR register which has the same encoding as the MIDR alias with opc2=4. So we only add that alias if we are not realizing a core that implements PMSA. Signed-off-by: Tobias Röhmel --- target/arm/helper.c | 13 + 1 file changed, 9 inser

[PATCH v5 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs

From: Tobias Röhmel RVBAR shadows RVBAR_ELx where x is the highest exception level if the highest EL is not EL3. This patch also allows ARMv8 CPUs to change the reset address with the rvbar property. Signed-off-by: Tobias Röhmel --- target/arm/cpu.c| 6 +- target/arm/helper.c | 21 +++

[PATCH v5 7/7] target/arm: Add ARM Cortex-R52 CPU

From: Tobias Röhmel All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 Signed-off-by: Tobias Röhmel --- target/arm/cpu_tcg.c | 42 ++ 1 file changed, 42 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c ind

[PATCH v5 6/7] target/arm: Add PMSAv8r functionality

From: Tobias Röhmel Add PMSAv8r translation. Signed-off-by: Tobias Röhmel --- target/arm/ptw.c | 127 +++ 1 file changed, 105 insertions(+), 22 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7d19829702..0514a83c1b 100644 --- a/t

[PATCH v4 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs

From: Tobias Röhmel RVBAR shadows RVBAR_ELx where x is the highest exception level if the highest EL is not EL3. This patch also allows ARMv8 CPUs to change the reset address with the rvbar property. Signed-off-by: Tobias Röhmel --- target/arm/cpu.c| 6 +- target/arm/helper.c | 23 +++

[PATCH v4 6/7] target/arm: Add PMSAv8r functionality

From: Tobias Röhmel Add PMSAv8r translation. Signed-off-by: Tobias Röhmel --- target/arm/ptw.c | 130 +++ 1 file changed, 110 insertions(+), 20 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4bd7389fa9..a5d890c09a 100644 --- a/t

[PATCH v4 3/7] target/arm: Make stage_2_format for cache attributes optional

From: Tobias Röhmel The v8R PMSAv8 has a two-stage MPU translation process, but, unlike VMSAv8, the stage 2 attributes are in the same format as the stage 1 attributes (8-bit MAIR format). Rather than converting the MAIR format to the format used for VMSA stage 2 (bits [5:2] of a VMSA stage 2 des

[PATCH v4 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32

From: Tobias Röhmel ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias Röhmel --- target/ar

[PATCH v4 1/7] target/arm: Don't add all MIDR aliases for cores that immplement PMSA

From: Tobias Röhmel Cores with PMSA have the MPUIR register which has the same encoding as the MIDR alias with opc2=4. So we only add that alias if we are not realizing a core that implements PMSA. Signed-off-by: Tobias Röhmel --- target/arm/helper.c | 14 ++ 1 file changed, 10 ins

[PATCH v4 5/7] target/arm: Add PMSAv8r registers

From: Tobias Röhmel Signed-off-by: Tobias Röhmel --- target/arm/cpu.c | 26 +++- target/arm/cpu.h | 12 ++ target/arm/helper.c | 290 +++ target/arm/machine.c | 28 + target/arm/ptw.c | 9 +- 5 files changed, 363 insertions(+), 2 del

[PATCH v4 0/7] Add ARM Cortex-R52 CPU

From: Tobias Röhmel Thanks again for all the help! Here is v4: 2. Made patch cleaner 3. Changed commit message 4. Replaced V8_R flag with ARM_FEATURE_PMSA|ARM_FEATURE_V8 5. Reworked the code to use existing pmsav7 variables Added migration support Added VSCTLR: I didn't add any functionality for

[PATCH v4 7/7] target/arm: Add ARM Cortex-R52 CPU

From: Tobias Röhmel All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 Signed-off-by: Tobias Röhmel --- target/arm/cpu_tcg.c | 42 ++ 1 file changed, 42 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c ind

[PATCH v3 8/9] target/arm: Add PMSAv8r functionality

From: Tobias Röhmel Add PMSAv8r translation. Signed-off-by: Tobias Röhmel --- target/arm/ptw.c | 171 +-- 1 file changed, 150 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c4f5721012..c7e37c66d0 100644 --- a/t

[PATCH v3 5/9] target/arm: Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup

From: Tobias Röhmel Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup to prepare for the Cortex-R52 MPU which uses and combines cache attributes of different translation levels. Signed-off-by: Tobias Röhmel --- target/arm/internals.h | 13 +++-- target/arm/m_helper.c | 3 ++- t

[PATCH v3 1/9] target/arm: Add ARM_FEATURE_V8_R

From: Tobias Röhmel This flag is necessary to add features for the Cortex-R52. Signed-off-by: Tobias Röhmel --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df677b2d5d..86e06116a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/c

[PATCH v3 2/9] target/arm: Don't add all MIDR aliases for cores that immplement PMSA

From: Tobias Röhmel Cores with PMSA have the MPUIR register which has the same encoding as the MIDR alias with opc2=4. So we only add that alias if we are not realizing a core that implements PMSA. Signed-off-by: Tobias Röhmel --- target/arm/helper.c | 14 ++ 1 file changed, 10 ins

[PATCH v3 9/9] target/arm: Add ARM Cortex-R52 cpu

From: Tobias Röhmel All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 Signed-off-by: Tobias Röhmel --- target/arm/cpu_tcg.c | 42 ++ 1 file changed, 42 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c ind

[PATCH v3 7/9] target/arm: Add PMSAv8r registers

From: Tobias Röhmel Signed-off-by: Tobias Röhmel --- target/arm/cpu.h| 10 +++ target/arm/helper.c | 171 2 files changed, 181 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 86e06116a9..632d0d13c6 100644 --- a/target/arm/c

[PATCH v3 3/9] target/arm: Make RVBAR available for all ARMv8 CPUs

From: Tobias Röhmel RVBAR shadows RVBAR_ELx where x is the highest exception level if the highest EL is not EL3. This patch also allows ARMv8 CPUs to change the reset address to be changed with the rvbar property. Signed-off-by: Tobias Röhmel --- target/arm/cpu.c| 6 +- target/arm/hel

[PATCH v3 4/9] target/arm: Make stage_2_format for cache attributes optional

From: Tobias Röhmel The Cortex-R52 has a 2 stage MPU translation process but doesn't have the FEAT_S2FWB feature. This makes it neccessary to allow for the old cache attribut combination. This is facilitated by changing the control path of combine_cacheattrs instead of failing if the second cache

[PATCH v3 0/9] Add ARM Cortex-R52 cpu

From: Tobias Röhmel Thanks for the review! Here is v3: v3: PATCH 2 (Don't add all MIDR aliases for cores that immplement PMSA): fixed the comment and changed to single element instead of array. Also the alias is not added for all PMSA CPUs as Peter suggested. PATCH 3 (Make RVBAR available for al

[PATCH v3 6/9] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32

From: Tobias Röhmel ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias Röhmel --- target/ar