On 2021/12/23 10:23, Stefan Berger wrote:
Add missing device identification objects _STR and _UID. They will appear
as files 'description' and 'uid' under Linux sysfs.
Cc: Shannon Zhao
Cc: Michael S. Tsirkin
Cc: Igor Mammedov
Cc: Ani Sinha
Fixes: https://gitlab.c
Hi,
On 2020/5/5 22:44, Eric Auger wrote:
+static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
+{
+hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
+PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
+MemoryRegion *sbdev_mr;
+SysBusDevice *sb
On 2020/3/12 1:20, Shameer Kolothum wrote:
diff --git a/docs/specs/acpi_hw_reduced_hotplug.rst
b/docs/specs/acpi_hw_reduced_hotplug.rst
index 911a98255b..e3abe975bf 100644
--- a/docs/specs/acpi_hw_reduced_hotplug.rst
+++ b/docs/specs/acpi_hw_reduced_hotplug.rst
@@ -63,6 +63,7 @@ GED IO interf
On 2019/3/12 17:10, Eric Auger wrote:
The GSIV numbers of the SPI based interrupts is not correct as
ARM_SPI_BASE was not added to the irqmap[VIRT_SMMU] value. So
this may collide with VIRTIO_MMIO irq window.
Signed-off-by: Eric Auger
Reviewed-by: Shannon Zhao
---
hw/arm/virt-acpi
kvm_arm_gic_realize early.
Signed-off-by: Shannon Zhao
---
hw/intc/arm_gic_kvm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index a611e8e..b4f2133 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -554,8 +554,9
On 2018/11/29 1:26, Auger Eric wrote:
struct AcpiIortSmmu3 {
ACPI_IORT_NODE_HEADER_DEF
uint64_t base_address;
@@ -639,6 +645,8 @@ struct AcpiIortSmmu3 {
uint32_t pri_gsiv;
uint32_t gerr_gsiv;
uint32_t sync_gsiv;
+ uint32_t pxm;
So if we use this field
On 2018/11/27 13:53, Auger Eric wrote:
Hi Shannon,
On 11/26/18 4:46 PM, Eric Auger wrote:
The AcpiIortSmmu3 misses 2 32b fields corresponding to the
proximity domain and the device id mapping index.
I fail to understand how we currently track the evolutions of the IORT
structures:
Looking
Hi,
On 2018/11/16 18:50, Peng Hao wrote:
Add pvpanic device in arm virt machine.
Signed-off-by: Peng Hao
Signed-off-by: Philippe Mathieu-Daudé
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/virt.c | 21 +
include/hw/arm/virt.h | 1 +
3
On 2018/11/2 17:35, Shannon Zhao wrote:
On 2018/11/1 18:22, Samuel Ortiz wrote:
We make the ARM virt ACPI code use the now shared build_rsdp() API from
aml-build.c. By doing so we fix a bug where the ARM implementation was
missing adding both the legacy and extended checksums, which was
On 2018/11/1 18:22, Samuel Ortiz wrote:
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 0a6a88380a..6822ee4eaa 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -546,7 +546,7 @@ build_srat(GArray *table_data, BIOSLinker *linker,
VirtMachineState *v
On 2018/11/1 18:22, Samuel Ortiz wrote:
We make the ARM virt ACPI code use the now shared build_rsdp() API from
aml-build.c. By doing so we fix a bug where the ARM implementation was
missing adding both the legacy and extended checksums, which was
building an invalid RSDP table.
Signed-off-by
Hi,
On 2018/11/1 18:22, Samuel Ortiz wrote:
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index f28a2faa53..0ed132b79b 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -367,7 +367,7 @@ static void acpi_dsdt_add_power_button(Aml *scope)
}
/* RSDP *
;t be found, or is unable to receive mail.
Note that the section still contains his personal email (see e59f13d76bb).
Signed-off-by: Philippe Mathieu-Daudé
Thanks Philippe.
Acked-by: Shannon Zhao
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
i
From: Shannon Zhao
Like commit 16b4226(hw/acpi-build: Add a check for memory-less NUMA node
), it also needs to check memory length for NUMA nodes on ARM.
Signed-off-by: Shannon Zhao
---
hw/arm/virt-acpi-build.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw
Hi,
On 8/28/2018 4:46 AM, Dongjiu Geng wrote:
This patch extends the qemu-kvm state sync logic with support for
KVM_GET/SET_VCPU_EVENTS, giving access to yet missing SError exception.
And also it can support the exception state migration.
Signed-off-by: Dongjiu Geng
---
change since v6:
1. Add
Hi Hongbo,
On 2018/7/25 13:30, Hongbo Zhang wrote:
> For the Aarch64, there is one machine 'virt', it is primarily meant to
> run on KVM and execute virtualization workloads, but we need an
> environment as faithful as possible to physical hardware, for supporting
> firmware and OS development for
On 2018/6/12 20:17, Paolo Bonzini wrote:
> On 16/05/2018 11:18, Shannon Zhao wrote:
>> According to KVM commit 75d61fbc, it needs to delete the slot before
>> changing the KVM_MEM_READONLY flag. But QEMU commit 235e8982 only check
>> whether KVM_MEM_READONLY flag is set in
Ping?
On 2018/5/16 17:18, Shannon Zhao wrote:
> According to KVM commit 75d61fbc, it needs to delete the slot before
> changing the KVM_MEM_READONLY flag. But QEMU commit 235e8982 only check
> whether KVM_MEM_READONLY flag is set instead of changing. It doesn't
> need to delet
On 2018/5/31 19:01, Auger Eric wrote:
> Hi,
>
> On 05/31/2018 05:15 AM, Shannon Zhao wrote:
>> While for_each_dist_irq_reg loop starts from GIC_INTERNAL, it forgot to
>> offset the date array and index. This will overlap the GICR registers
>> value and leave
migration source (old version
qemu) doesn't send gicd_no_migration_shift_bug = 1 to destination, then
we shift the data of PPI to get the right data for SPI.
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-sta...@nongnu.org
Reviewed-by: Eric Auger
Reviewed-by: Peter Maydell
Signed-
2018-05-31 21:50 GMT+08:00 Peter Maydell :
> On 31 May 2018 at 04:15, Shannon Zhao wrote:
> > While we skip the GIC_INTERNAL irqs, we don't change the register offset
> > accordingly. This will overlap the GICR registers value and leave the
> > last GIC_INTERNAL irq
On 2018/5/31 15:54, Auger Eric wrote:
> Hi Shannon,
>
> On 05/31/2018 09:16 AM, Shannon Zhao wrote:
>> kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
>> initialize global capability variables. If we call kvm_init_irq_routing in
>> GIC
kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
initialize global capability variables. If we call kvm_init_irq_routing in
GIC realize function, previous allocated memory will leak.
Fix this by deleting the unnecessary call.
Signed-off-by: Shannon Zhao
---
hw/intc
migration source (old version
qemu) doesn't send gicd_no_migration_shift_bug = 1 to destination, then
we shift the data of PPI to get the right data for SPI.
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-sta...@nongnu.org
Signed-off-by: Shannon Zhao
---
hw/intc/arm_gicv3_common
the data
Shannon Zhao (2):
arm_gicv3_kvm: kvm_dist_get/put_priority: skip the registers banked by
GICR_IPRIORITYR
arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR
hw/intc/arm_gicv3_common.c | 79 ++
hw/intc/arm_gicv3_kvm.c
ed-by: Peter Maydell
Signed-off-by: Shannon Zhao
---
hw/intc/arm_gicv3_kvm.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 3536795..147e691 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw
On 2018/5/31 0:18, Laszlo Ersek wrote:
> +vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
>> +
Does it need a info log here to tell user that even though you enable
the highmem_ecam but due to some other reasons it's disabled.
Also, if user enables highmem_ecam but final
->node_offset
for subsequent computations that will result incorrect value if host is
not litlle endian. So use the non-converted one instead.
Signed-off-by: Shannon Zhao
---
V3: Fix typo and add some words in commit message to explain another bug
---
hw/arm/virt-acpi-build.c | 20 +++-
Hi Eric,
On 2018/5/30 14:38, Auger Eric wrote:
> I checked against the v1 in my branch thinking you did not change
> anything besides the comment (your log history?).
Sorry about this, I'll add some words in commit message.
Thanks,
--
Shannon
On 2018/5/29 22:44, Peter Maydell wrote:
> On 25 May 2018 at 12:22, Shannon Zhao wrote:
>> While we skip the GIC_INTERNAL irqs, we don't change the register offset
>> accordingly. This will overlap the GICR registers value and leave the
>> last GIC_INTERNAL irq
On 2018/5/30 3:53, Auger Eric wrote:
> Hi Shannon,
>
> On 05/29/2018 04:09 PM, Shannon Zhao wrote:
>>
>>
>>> 在 2018年5月29日，21:53，Peter Maydell 写道：
>>>
>>>> On 29 May 2018 at 04:08, Shannon Zhao wrote:
>>>> acpi_data_push uses
> 在 2018年5月29日，21:53，Peter Maydell 写道：
>
>> On 29 May 2018 at 04:08, Shannon Zhao wrote:
>> acpi_data_push uses g_array_set_size to resize the memory size. If there
>> is no enough contiguous memory, the address will be changed. So previous
>> pointer could
Signed-off-by: Shannon Zhao
---
V2: add comments for iort_node_offset and reviewed tags
---
hw/arm/virt-acpi-build.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 92ceee9..6209138 100644
--- a/hw/arm
acpi_data_push uses g_array_set_size to resize the memory size. If there
is no enough contiguous memory, the address will be changed. So previous
pointer could not be used any more. It must update the pointer and use
the new one.
Signed-off-by: Shannon Zhao
---
hw/arm/virt-acpi-build.c | 14
On 2018/5/25 19:36, no-re...@patchew.org wrote:
> /tmp/qemu-test/src/hw/intc/arm_gicv3_common.c: In function
> 'gicv3_gicd_no_migration_shift_bug_post_load':
> /tmp/qemu-test/src/hw/intc/arm_gicv3_common.c:165:9: error:
> 'gicd_no_migration_shift_bug' undeclared (first use in this function); di
These two patches fix ARM KVM GICv3 get/put data shift bug and add
compatibility fro migration from old qemu to new one.
Major Changes in V4:
* Fix the kvm_dist_get/put_priority in a separate patch since it doesn't
need migration compatibility.
* Fix the data within post-load function
Sh
d-off-by: Shannon Zhao
---
hw/intc/arm_gicv3_kvm.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 3536795..147e691 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -135,7 +1
migration source (old version
qemu) doesn't send gicd_no_migration_shift_bug = 1 to destination, then
we shift the data of PPI to get the right data for SPI.
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-sta...@nongnu.org
Signed-off-by: Shannon Zhao
---
hw/intc/arm_gicv3_common
On 2018/5/24 21:11, Peter Maydell wrote:
> On 23 May 2018 at 04:53, Shannon Zhao wrote:
>> While we skip the GIC_INTERNAL irqs, we don't change the register offset
>> accordingly. This will overlap the GICR registers value and leave the
>> last GIC_INTERNAL irq
On 2018/5/24 22:56, Peter Maydell wrote:
> On 24 May 2018 at 15:40, Auger Eric wrote:
>> > Hi Peter,
>> >
>> > On 05/24/2018 04:16 PM, Peter Maydell wrote:
>>> >> Only for KVM, not for TCG, and it's the other way round: we
>>> >> end up with two lots of PPI/SGI space in the data structure
>>> >>
On 2018/5/24 17:04, Auger Eric wrote:
> Hi Shannon,
>
> On 05/23/2018 05:53 AM, Shannon Zhao wrote:
>> While we skip the GIC_INTERNAL irqs, we don't change the register offset
>> accordingly. This will overlap the GICR registers value and leave the
>> last GIC
On 2018/5/22 17:13, Peter Maydell wrote:
> On 8 April 2018 at 02:50, Shannon Zhao wrote:
>> On 2018/4/6 17:36, Peter Maydell wrote:
>>> On reflection, I think I'd aim for 2.13 for this, since:
>>> * it's not a regression
>>> * it doesn't act
migration source (old version
qemu) doesn't send gicd_no_shift_bug = 1 to destination, then we shift
the data of PPI to get the right data for SPI.
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-sta...@nongnu.org
Signed-off-by: Shannon Zhao
---
Changes in V3: add migration compatibili
It forgot to increase clroffset during the loop. So it only clear the
first 4 bytes.
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-sta...@nongnu.org
Signed-off-by: Shannon Zhao
Reviewed-by: Eric Auger
---
Changes in V3: Add reviewed-by tag
---
hw/intc/arm_gicv3_kvm.c | 1 +
1 file
n abort to guest due to the broken hva, then
guest will get stuck.
Signed-off-by: Shannon Zhao
---
include/sysemu/kvm_int.h | 1 +
kvm-all.c| 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
index 888557
On 2018/4/6 17:36, Peter Maydell wrote:
> On 5 April 2018 at 15:22, Peter Maydell wrote:
>> > On 29 March 2018 at 11:54, Peter Maydell wrote:
>>> >> On 23 March 2018 at 12:08, Peter Maydell
>>> >> wrote:
>>>> >>> On 21 March 201
On 2018/3/27 22:15, Eric Auger wrote:
> With KVM acceleration and if KVM VGICV3 supports to set multiple
> redistributor regions, we now allow up to 512 vcpus.
>
> Signed-off-by: Eric Auger
> ---
> hw/arm/virt.c | 17 -
> include/hw/arm/virt.h | 1 +
> 2 files changed,
On 2018/3/20 16:42, Auger Eric wrote:
> Hi Shannon,
> On 20/03/18 08:26, Shannon Zhao wrote:
>> While we skip the GIC_INTERNAL irqs, we don't change the register offset
>> accordingly. This will overlap the GICR registers value and leave the
>> last GIC_INTERNAL
On 2018/3/20 19:54, Peter Maydell wrote:
> On 20 March 2018 at 11:36, Shannon Zhao wrote:
>>
>>
>> On 2018/3/20 19:22, Peter Maydell wrote:
>>> On 20 March 2018 at 07:26, Shannon Zhao wrote:
>>>> While we skip the GIC_INTERNAL irqs, we don't ch
On 2018/3/20 19:22, Peter Maydell wrote:
> On 20 March 2018 at 07:26, Shannon Zhao wrote:
>> While we skip the GIC_INTERNAL irqs, we don't change the register offset
>> accordingly. This will overlap the GICR registers value and leave the
>> last GIC_INTERNAL irq
While we skip the GIC_INTERNAL irqs, we don't change the register offset
accordingly. This will overlap the GICR registers value and leave the
last GIC_INTERNAL irq's registers out of update.
Fix this by skipping the registers banked by GICR.
Signed-off-by: Shannon Zhao
--
It forgot to increase clroffset during the loop. So it only clear the
first 4 bytes.
Signed-off-by: Shannon Zhao
---
hw/intc/arm_gicv3_kvm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index ec37177..3536795 100644
--- a/hw/intc
Changes in V2:
* patch 1 use the existing variable
* patch 2 add more comments to explain the problem
Shannon Zhao (2):
arm_gicv3_kvm: increase clroffset accordingly
arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR
hw/intc/arm_gicv3_kvm.c | 39
to_le32(2); /* RC and ITS nodes */
>> +iort->node_count = cpu_to_le32(nb_nodes);
>> iort->node_offset = cpu_to_le32(sizeof(*iort));
>>
>> /* ITS group node */
>> @@ -418,6 +425,35 @@ build_iort(GArray *table_data, BIOSLinker *linker)
>> its->its_cou
Shannon Zhao (2):
arm_gicv3_kvm: increase clroffset accordingly
arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR
hw/intc/arm_gicv3_kvm.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
--
2.0.4
It forgot to increase clroffset during the loop. So it only clear the
first 4 bytes.
Signed-off-by: Shannon Zhao
---
hw/intc/arm_gicv3_kvm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index ec37177..7000716 100644
It should skip to getting/putting the registers banked by GICR so that
it could get/put the correct ones.
Signed-off-by: Shannon Zhao
---
hw/intc/arm_gicv3_kvm.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 7000716
From: Zhaoshenglong
acpi_data_push uses g_array_set_size to resize the memory size. If there
is no enough contiguous memory, the address will be changed. If we use
the old value, it will assert.
qemu-kvm: hw/acpi/bios-linker-loader.c:214: bios_linker_loader_add_checksum:
Assertion `start_offset <
From: Zhaoshenglong
acpi_data_push uses g_array_set_size to resize the memory size. If there
is no enough contiguous memory, the address will be changed. If we use
the old value, it will assert.
qemu-kvm: hw/acpi/bios-linker-loader.c:214: bios_linker_loader_add_checksum:
Assertion `start_offset <
On 2017/12/26 19:48, Andrew Jones wrote:
> On Fri, Dec 22, 2017 at 02:52:47PM +0800, Shannon Zhao wrote:
>> acpi_data_push uses g_array_set_size to resize the memory size. If there is
>> no
>> enough contiguous memory, the address will be changed. If we use the old
>&g
b->len' failed.`
Signed-off-by: Shannon Zhao
---
hw/arm/virt-acpi-build.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 3d78ff6..5901142 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/vir
On 2017/12/12 14:54, Yang Zhong wrote:
>> > 2) what effect it has on boot time in Shannon's case.
> Hello Shannon,
>
> It's hard for me to reproduce your commands in my x86 enviornment, as a
> compare test,
> would you please help me use above two TEMP patches to verify VM bootup
> time
On 2017/12/12 14:54, Yang Zhong wrote:
>> 2) what effect it has on boot time in Shannon's case.
> Hello Shannon,
>
> It's hard for me to reproduce your commands in my x86 enviornment, as a
> compare test,
> would you please help me use above two TEMP patches to verify VM bootup
> time ag
00644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -543,7 +543,7 @@ F: include/hw/*/xlnx*.h
ARM ACPI Subsystem
M: Shannon Zhao
-M: Shannon Zhao
+M: Shannon Zhao
L: qemu-...@nongnu.org
S: Maintained
F: hw/arm/virt-acpi-build.c
--
2.0.4
On 2017/12/8 23:02, Peter Maydell wrote:
> Currently we only provide one non-secure UART on the virt
> board. This is OK for most purposes, but there are some
> use cases where having a second UART would be useful (like
> bare-metal testing where you don't really want to have to
> probe and set u
ART] + ARM_SPI_BASE));
> +if (!vmc->no_second_uart) {
> +acpi_dsdt_add_uart(scope, &memmap[VIRT_UART_2],
> + (irqmap[VIRT_UART_2] + ARM_SPI_BASE));
> +}
> acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
> acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
> acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
>
Reviewed-by: Shannon Zhao
--
Shannon
Hi Yang,
On 2017/12/4 20:03, Yang Zhong wrote:
> On Fri, Dec 01, 2017 at 01:52:49PM +0100, Paolo Bonzini wrote:
>> > On 01/12/2017 11:56, Yang Zhong wrote:
>>> > > This issue should be caused by much times of system call by
>>> > > malloc_trim(),
>>> > > Shannon's test script include 60 scsi
Hi,
On 2017/11/24 14:30, Yang Zhong wrote:
> Since there are some issues in memory alloc/free machenism
> in glibc for little chunk memory, if Qemu frequently
> alloc/free little chunk memory, the glibc doesn't alloc
> little chunk memory from free list of glibc and still
> allocate from OS, which
The virtio-gpu is not Linux specific. If windows could include the
device driver, it can be used on windows as well like other virtio
devices on windows x86.
I'm not sure what's the requirements for booting Windows on ARM64 virt
machine since the OS is not open source. So it would be better someon
"D:\Program Files\qemu\qemu-system-aarch64.exe" -device virtio-scsi-
pci,id=scsi -drive if=none,id=cd,file=\path\to\iso -device scsi-
cd,drive=cd,bootindex=0 -m 2048 -cpu cortex-a57 -smp 4 -machine virt
-device virtio-gpu-pci -bios "QEMU_EFI .fd" -device usb-ehci -device
usb-kbd -device usb-mouse -
On 2017/8/25 19:20, gengdongjiu wrote:
>>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>>> >> index 3d78ff6..def1ec1 100644
>>> >> --- a/hw/arm/virt-acpi-build.c
>>> >> +++ b/hw/arm/virt-acpi-build.c
>>> >> @@ -45,6 +45,7 @@
>>> >> #include "hw/arm/virt.h"
>>> >> #include "
On 2017/8/25 18:37, gengdongjiu wrote:
>>> +
>>> >> +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */
>>> >> +
>> > It's better to refer to the first spec version of this structure and
>> > same with others you define.
> do you mean which spec version? the definition is align
On 2017/8/18 22:23, Dongjiu Geng wrote:
> Add CONFIG_ACPI_APEI configuration in the Makefile and
> enable it in the arm-softmmu.mak
>
> Signed-off-by: Dongjiu Geng
> ---
> default-configs/arm-softmmu.mak | 1 +
> hw/acpi/Makefile.objs | 1 +
> 2 files changed, 2 insertions(+)
>
> di
On 2017/8/18 22:23, Dongjiu Geng wrote:
> This implements APEI GHES Table by passing the error CPER info
> to the guest via a fw_cfg_blob. After a CPER info is recorded, an
> SEA(Synchronous External Abort)/SEI(SError Interrupt) exception
> will be injected into the guest OS.
>
> Below is the ta
On 2017/8/18 22:23, Dongjiu Geng wrote:
> (1) Add related APEI/HEST table structures and macros, these
> definition refer to ACPI 6.1 and UEFI 2.6 spec.
> (2) Add generic error status block and CPER memory section
> definition, user space only handle memory section errors.
>
> Signed-of
On 2017/4/14 20:46, Eric Auger wrote:
[...]
> @@ -43,6 +50,7 @@ struct GICv3ITSState {
>
> /* Registers */
> uint32_t ctlr;
> +uint32_t iidr;
I think this should reset in gicv3_its_common_reset
Thanks,
--
Shannon
On 2017/5/30 1:37, Andrew Jones wrote:
> Cc: Shannon Zhao
> Signed-off-by: Andrew Jones
Reviewed-by: Shannon Zhao
> ---
> hw/arm/virt-acpi-build.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
On 2017/5/30 1:37, Andrew Jones wrote:
> This is based on patch Shannon Zhao originally posted.
>
> Cc: Shannon Zhao
> Signed-off-by: Andrew Jones
Reviewed-by: Shannon Zhao
> ---
> hw/arm/virt.c | 21 +
> 1 file changed, 21 insertions(+)
>
>
On 2017/4/14 20:46, Eric Auger wrote:
> We change the restoration priority of both the GICv3 and ITS. The
> GICv3 must be restored before the ITS and the ITS needs to be restored
> before PCIe devices since it translates their MSI transactions.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Juan
On 2017/4/24 18:16, Marcel Apfelbaum wrote:
> On 04/24/2017 01:02 PM, Laszlo Ersek wrote:
>> On 04/14/17 04:41, Shannon Zhao wrote:
>>> Hi Laszlo,
>>>
>>> Thanks a lot for your reply:)
>>>
>>> On 2017/4/14 1:09, Laszlo Ersek wrote:
>>&g
Hi Laszlo,
Thanks a lot for your reply:)
On 2017/4/14 1:09, Laszlo Ersek wrote:
> Adding Andrea, Ard, Drew and Marcel; and the main qemu list
>
> On 04/13/17 09:37, Shannon Zhao wrote:
>> Hi,
>>
>> I'm testing the PCIe devices hotplug for ARM virt machine and
+
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Shannon Zhao
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 8955a9d..0835e59 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -90,6 +90,7 @@ static void acpi_dsdt
file changed, 1 insertion(+)
>
Reviewed-by: Shannon Zhao
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 07a10ac..8955a9d 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -135,6 +135,7 @@ static void acpi_dsdt_add_virtio(
From: Shannon Zhao
For ARM virt machine, if we use virt-2.7 which will not create ITS node,
the virtio-net can not recieve interrupts so it can't get ip address
through dhcp.
This fixes commit 83d768b(virtio: set ISR on dataplane notifications).
Signed-off-by: Shannon Zhao
---
V2: Factor
From: Shannon Zhao
For ARM virt machine, if we use virt-2.7 which will not create ITS node,
the virtio-net can not recieve interrupts so it can't get ip address
through dhcp.
This fixes commit 83d768b(virtio: set ISR on dataplane notifications).
Signed-off-by: Shannon Zhao
---
hw/v
From: Shannon Zhao
For example, using -cpu generic will cause qemu segmentation fault.
Signed-off-by: Shannon Zhao
---
V2: Just remove the member NULL instead of checking twice
---
hw/arm/virt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 7a03f84
On 2017/1/17 1:27, Peter Maydell wrote:
> On 15 January 2017 at 10:51, Shannon Zhao wrote:
>> From: Shannon Zhao
>>
>> For example, using -cpu generic will cause qemu segmentation fault.
>>
>> Signed-off-by: Shannon Zhao
>> ---
>> hw/arm/virt.c
From: Shannon Zhao
This patch set support use cross type vCPU when using KVM on ARM and add
two new CPU types: generic and cortex-a72.
You can test this patch set with QEMU using
-cpu cortex-a53/cortex-a57/generic/cortex-a72
These patches can be fetched from:
https://git.linaro.org/people
From: Shannon Zhao
Signed-off-by: Shannon Zhao
---
target/arm/kvm-consts.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
index a2c9518..fc01ac5 100644
--- a/target/arm/kvm-consts.h
+++ b/target/arm/kvm-consts.h
@@ -128,6 +128,7
From: Shannon Zhao
If user requests a specific type vCPU which is not same with the
physical ones and if kvm supports cross type vCPU, we set the
KVM_ARM_VCPU_CROSS bit and set the CPU ID registers.
Signed-off-by: Shannon Zhao
---
target/arm/kvm64.c | 182
From: Shannon Zhao
Add a generic type cpu, it's useful for migration when running on
different hardwares.
Signed-off-by: Shannon Zhao
---
target/arm/cpu64.c | 54 ++
1 file changed, 54 insertions(+)
diff --git a/target/arm/cpu64.c b/t
From: Shannon Zhao
Signed-off-by: Shannon Zhao
---
hw/arm/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4b301c2..49b7b65 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -166,6 +166,7 @@ static const char *valid_cpus[] = {
"corte
From: Shannon Zhao
Signed-off-by: Shannon Zhao
---
linux-headers/asm-arm64/kvm.h | 1 +
linux-headers/linux/kvm.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
index fd5a276..f914eac 100644
--- a/linux-headers/asm-arm64
From: Shannon Zhao
Add the ARM Cortex-A72 processor definition. It's similar to A57.
Signed-off-by: Shannon Zhao
---
hw/arm/virt.c | 1 +
target/arm/cpu64.c | 56 ++
2 files changed, 57 insertions(+)
diff --git a/hw/arm/virt.c
From: Shannon Zhao
For example, using -cpu generic will cause qemu segmentation fault.
Signed-off-by: Shannon Zhao
---
hw/arm/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 7a03f84..4b301c2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm
ice("C%03x", i);
> +Aml *dev = aml_device("C%.03X", i);
> aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
> aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> aml_append(scope, dev);
>
Reviewed-by: Shannon Zhao
Thanks,
--
Shannon
Hi guys,
Looking at the codes, for pc-2.4 machine it enables host-cache-info for
guest so guest can get the L3 cache info of host. But since QEMU has its
own rule to generate ACPI ID, guest will not use the L3 cache correctly.
I also notice that QEMU present L1 and L2 cache for guest via its own
From: Shannon Zhao
Enable cortex-a72 cpu support for KVM.
Signed-off-by: Shannon Zhao
---
linux-headers/asm-arm64/kvm.h | 3 ++-
target-arm/cpu64.c| 1 +
target-arm/kvm-consts.h | 2 ++
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/linux-headers/asm-arm64
From: Shannon Zhao
Add the ARM Cortex-A72 processor definition. It's similar to A57.
Signed-off-by: Shannon Zhao
---
target-arm/cpu64.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
From: Shannon Zhao
This series add cortex-a72 cpu support for target-arm.
Shannon Zhao (3):
target-arm: cpu64: Add support for Cortex-A72
target-arm/kvm64: Add cortex-a72 cpu support
hw/arm/virt: Add cortex-a72 cpu support in machine virt
hw/arm/virt.c | 5
linux
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