I tried your fix. Yes, the fpscr and mvfr0/1/2 values do match the FVP,
now (except for the MVE bit which is explained above).
Thx for the updates.
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https://bugs.launchpad.net/bugs/19238
I changed the compile options to single precision, only. Then, my small
FP example works. Ok for my purposes, I don't need double.
But I would need MVE. Are there any plans to implement MVE?
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Thanks for the fix. I applied it and
1. yes, the hard fault when reading FPSCR is gone.
2. yes, I also see the UNDEF. Note that on the Corstone-300 MPS3-AN547 FVP I
can access mvfr0 via vmrs.
I changed the vmrs to ldr. Now I can read the registers. The values differ from
what the FVP tells me:
f
Command line is
qemu-system-arm -machine mps3-an547 -nographic -kernel test.elf -semihosting
-semihosting-config enable=on,target=native
Binary is attached. It does
int main(int argc, char* argv[])
{
SCB->NSACR |= (3U << 10U);/* enable Non-secure access to
CP10 and CP11 copr
Yes, I think I did:
SCB->NSACR |= (3U << 10U);/* enable Non-secure access to
CP10 and CP11 coprocessors */
__DSB();
__ISB();
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full A
** Description changed:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel .elf
-semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-WSL2
#1 SMP Wed Oct 28 23
Public bug reported:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel .elf
-semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-WSL2
#1 SMP Wed Oct 28 23:40:43 UTC 2020 x
