[Qemu-devel] [PATCH v3] target/ppc: Allow PIR read in privileged mode

According to PowerISA, the PIR register should be readable in privileged mode also, not only in hypervisor privileged mode. PowerISA 3.0 - 4.3.3 Processor Identification Register "Read access to the PIR is privileged; write access is not provided." Cc: David Gibson Cc: Alexander Graf Cc: qemu-

[Qemu-devel] [PATCH] Allow PIR read in privileged mode

According to PowerISA, the PIR register should be readable in privileged mode also, not only in hypervisor privileged mode. Cc: David Gibson Cc: Alexander Graf Cc: qemu-...@nongnu.org Signed-off-by: Leandro Lupori Reviewed-by: Jose Ricardo Ziviani --- target/ppc/translate_init.c | 2 +- 1 fil