Re: [RFC 00/10] add the rest of riscv bitmapip-0.93 instructions

Ok, thanks. ^ ^! Alistair Francis 于2021年9月24日周五 下午12:39写道： > On Sat, Sep 18, 2021 at 6:20 PM Eric Tang > wrote: > > > > These patches fixed some issues about srow/sroiw/clzw instructions and > > add the rest of riscv bitmapip-0.93 instructions except fsri/fsriw &

[RFC 06/10] target/riscv: rvb: add bfp/bfpw instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index fa4597b44b..35f7b0926b 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -245,3 +245,30 @@ target_ulong HELPER(xperm_w)(target_ulong rs1, target_ulong

[RFC 10/10] target/riscv: rvb: add funnel shfit instructions

Add funnel shfit instructions except fsri/fsriw for opcode ecoding reason. Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index e936444c12..08a2fbb376 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c

[RFC 05/10] target/riscv: rvb: add crossbar permutation instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 19c64756c5..fa4597b44b 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -205,3 +205,43 @@ target_ulong HELPER(unshflw)(target_ulong rs1, target_ulong

[RFC 08/10] target/riscv: rvb: add bit-matrix instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 469145ffa9..e936444c12 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -327,3 +327,78 @@ target_ulong HELPER(crc32c_d)(target_ulong rs1) { return

[RFC 09/10] target/riscv: rvb: fixed an issue about clzw instruction

Signed-off-by: Eric Tang diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 39ca5a573f..4523a5cd4c 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -456,7 +456,7 @@ GEN_TRANS_SHADD(3

[RFC 02/10] target/riscv: rvb: add carry-less multiply instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 5b2f795d03..e31cf582ca 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -88,3 +88,38 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2

[RFC 07/10] target/riscv: rvb: add CRC instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index 35f7b0926b..469145ffa9 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -272,3 +272,58 @@ target_ulong HELPER(bfpw)(target_ulong rs1, target_ulong rs2

[RFC 04/10] target/riscv: rvb: add generalized shuffle instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index e31cf582ca..19c64756c5 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -123,3 +123,85 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2

[RFC 01/10] target/riscv: rvb: fixed an error about srow/sroiw instructions

According to spec, these instructions ignore the upper 32 bit of their input and sign-extend their 32 bit output values. Fixed the output's error when their input values greater than 0x. Signed-off-by: Eric Tang diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/t

[RFC 03/10] target/riscv: rvb: add cmix/cmov instructions

Signed-off-by: Eric Tang diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9eff9d5f5c..989ea3c602 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -43,6 +43,7 @@ &rrd rs1 rs2 &r2 rd rs1 &r2_s rs1 rs2 +&r4 rd rs1 rs

[RFC 00/10] add the rest of riscv bitmapip-0.93 instructions

bitmapip instructions, passed by compare the results that produced by qemu and spike. Please review and give your opinion kindly :) Eric Tang (10): target/riscv: rvb: fixed an error about srow/sroiw instructions target/riscv: rvb: add carry-less multiply instructions target/riscv: rvb: add c