[RFC PATCH v2] target/i386: add support for VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE

VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE support, and sets up dependency between the bit and CPUID_7_0_ECX_WAITPKG. QEMU should not expose waitpkg feature if VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE is not available to avoid unexpected invalid opcode exception in L2 guests. Signed-off-by: Ake Koomsin --- v2: - Fix typo in the

[RFC PATCH] targer/i386: add support for VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE

VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE support, and sets up dependency between the bit and CPUID_7_0_ECX_WAITPKG. QEMU should not expose waitpkg feature if VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE is not available to avoid unexpected invalid opcode exception in L2 guests. Signed-off-by: Ake Koomsin --- target/i386/cpu.c | 6

[PATCH v3] target/arm: honor HCR_E2H and HCR_TGE in ats_write64()

We need to check HCR_E2H and HCR_TGE to select the right MMU index for the correct translation regime. To check for EL2&0 translation regime: - For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE - For S1E2* ops, check only HCR_E2H Signed-off-by: Ake Koomsin --- v3: - A

[PATCH v2] target/arm: honor HCR_E2H and HCR_TGE in ats_write64()

We need to check HCR_E2H and HCR_TGE to select the right MMU index for the correct translation regime. To check for EL2&0 translation regime: - For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE - For S1E2* ops, check only HCR_E2H Signed-off-by: Ake Koomsin --- v2: - Rebase

Re: [PATCH] target/arm: honor HCR_E2H for AT S1E2R and AT S1E2W address translation

On Tue, 25 Oct 2022 13:25:22 +0100 Peter Maydell wrote: > On Mon, 17 Oct 2022 at 10:30, Ake Koomsin wrote: > > > > When HCR_E2H is set, AT S1E2R and AT S1E2W should translate an > > address based on both TTBR0_EL2 and TTBR1_EL2. > > > > Signed-off-by: Ake

Re: [PATCH] target/arm: honor HCR_E2H and HCR_TGE in arm_excp_unmasked()

On Tue, Oct 25, 2022 at 1:37 AM Peter Maydell wrote: > On Mon, 17 Oct 2022 at 10:29, Ake Koomsin wrote: > > > > An exception targeting EL2 from lower EL is actually maskable when > > HCR_E2H and HCR_TGE are both set. This applies to both secure and > > non-secure Sec

[PATCH] target/arm: honor HCR_E2H and HCR_TGE in arm_excp_unmasked()

An exception targeting EL2 from lower EL is actually maskable when HCR_E2H and HCR_TGE are both set. This applies to both secure and non-secure Security state. Signed-off-by: Ake Koomsin --- target/arm/cpu.c | 24 +--- 1 file changed, 17 insertions(+), 7 deletions(-) diff

[PATCH] target/arm: honor HCR_E2H for AT S1E2R and AT S1E2W address translation

When HCR_E2H is set, AT S1E2R and AT S1E2W should translate an address based on both TTBR0_EL2 and TTBR1_EL2. Signed-off-by: Ake Koomsin --- target/arm/helper.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index dde64a487a

[PATCH] e1000e: Fix possible interrupt loss when using MSI

ling timer. The guest can then receive interrupts eventually. Signed-off-by: Ake Koomsin --- hw/net/e1000e_core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 2c51089a82..208e3e0d79 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e10