On 21/01/2025 18.16, Jonathan Cameron wrote:
> On Thu, 12 Dec 2024 05:04:22 -0800
> Zhi Wang wrote:
>
>> From: Zhi Wang
>>
>> Introduce a CXL type-2 device emulation that provides a minimum base for
>> testing kernel CXL core type-2 support and CXL type-2 vir
On 21/01/2025 17.34, Jonathan Cameron wrote:
> On Thu, 12 Dec 2024 18:10:10 +
> Zhi Wang wrote:
>
>> On 12/12/2024 18.49, Alejandro Lucero Palau wrote:
>>>
>>> On 12/12/24 13:04, Zhi Wang wrote:
>>>> Hi folks:
>>>>
>>>>
On 12/12/2024 19.02, Alejandro Lucero Palau wrote:
>
> On 12/12/24 13:04, Zhi Wang wrote:
>> From: Zhi Wang
>>
>> Introduce a CXL type-2 device emulation that provides a minimum base for
>> testing kernel CXL core type-2 support and CXL type-2 virtualization.
On 12/12/2024 18.49, Alejandro Lucero Palau wrote:
>
> On 12/12/24 13:04, Zhi Wang wrote:
>> Hi folks:
>>
>> Per the discussion with Ira/Jonathan in the LPC 2024 and in the CXL
>> discord channel, we are trying to introduce a CXL type-2 device emulation
>> in
From: Zhi Wang
Introduce a CXL type-2 device emulation that provides a minimum base for
testing kernel CXL core type-2 support and CXL type-2 virtualization. It
is also a good base for introducing the more emulated features.
Currently, it only supports:
- Emulating component registers with HDM
type-3 device.
No functional change is intended.
Signed-off-by: Zhi Wang
---
hw/cxl/cxl-component-utils.c | 65 ++
hw/mem/cxl_type3.c | 61 +--
include/hw/cxl/cxl_component.h | 3 ++
3 files changed, 69 insertions(+), 60
://www.youtube.com/watch?v=e5OW1pR84Zs
[3] https://lore.kernel.org/kvm/20240920223446.1908673-3-z...@nvidia.com/T/
[4] https://youtu.be/zlk_ecX9bxs?si=pf9CttcGT5KwUgiH
[5]
https://lore.kernel.org/linux-cxl/20241212123959.68514-1-z...@nvidia.com/T/#u
Zhi Wang (3):
hw/cxl: factor out
via:
pciehp_reset_slot+0xa8/0x150
Introduce cxl_component_update_dvsec() for the emulation of CXL devices
to reset the CXL DVSEC registers in the PCI configuration space.
Signed-off-by: Zhi Wang
---
hw/cxl/cxl-component-utils.c | 36 --
include/hw/cxl
On 17/10/2024 19.57, Cédric Le Goater wrote:
> External email: Use caution opening links or attachments
>
>
> Hello,
>
> On 5/18/23 04:45, Ira Weiny wrote:
>> Type 2 devices are not yet a reality. Developing core kernel support
>> is difficult without some test device to model against.
>>
>> De
To support CXL device passthrough, vfio-cxl-core is introduced. This
is the QEMU part.
Get the CXL caps from the vfio-cxl-core. Trap and emulate the HDM
decoder registers. Map the HDM decdoers when the guest commits a HDM
decoder.
Signed-off-by: Zhi Wang
---
hw/vfio/common.c | 3
(patches, repos, kernel config) all what you need to test
and hack around, plus a demo video shows the kernel/QEMU command line
can be found at:
https://lore.kernel.org/kvm/20240920223446.1908673-7-z...@nvidia.com/T/
Zhi Wang (1):
vfio: support CXL device in VFIO stub
hw/vfio/common.c
It's nice to see cloud vendors are also quite interested in VFIO
migration interfaces and functions. From what Yan said and Huawei's
requirements, there should be more devices which don't have private
memory, maybe GPU is almost the only one which has the private memory.
As VFIO is a generic u
Remove extra quirks, old definitions and functions. Once the new Intel
platform definition is introduced, and the PA of guest stolen memory
equals to the PA of host stolen memory, they are not necessary anymore.
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/pci-quirks.c | 209
Hi Alex:
This the RFC patch of my ides in previous email. Could you shed
some lights here? :)
Thanks,
Zhi.
On 05/30/17 01:30, Zhi Wang wrote:
This patch series are aim to refine the IGD stolen memory support in QEMU.
Some features of Intel HW relies on the stolen memory to work, but
Also setup IGD stolen memory under secondary mode as some HW functions
might need the stolen memory anyway.
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/pci-quirks.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/hw/vfio/pci-quirks.c b
Clear the whole GGTT page tables after the quirk is initialized. Obtain
the total size of GGTT and the entry size of one GGTT entry from
intel_device_info().
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/pci-quirks.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions
Also setup IGD stolen memory under secondary mode as some HW functions
might need the stolen memory anyway.
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/pci-quirks.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/hw/vfio/pci-quirks.c b
Initialize IGD quirks a bit earlier since we're going to support IGD
stolen memory under both primary mode (legacy mode) and secondary mode
and we need one extra memory region from IGD quirks.
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/pci-quirks.c
memory region will be marked as reserved in guest E820 table.
We don't need to take care of GGMS, as the accesses to GGMS from HW bypass
IOMMU.
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/pci-quirks.c | 83 ++--
1 file change
form definitions and clears some old funtions
and definitions.
Zhi Wang (6):
vfio: Add Intel platform definitions
vfio: Setup IGD quirks earlier
vfio: Setup IGD stolen memory
vfio: Refine GGTT clearing
vfio: Remove extra quirks and old definitions
vfio: Setup IGD stolen memory under seco
Remove extra quirks, old definitions and functions. Once the new Intel
platform definition is introduced, and the PA of guest stolen memory
equals to the PA of host stolen memory, they are not necessary anymore.
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/pci-quirks.c | 209
Clear the whole GGTT page tables after the quirk is initialized. Obtain
the total size of GGTT and the entry size of one GGTT entry from
intel_device_info().
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/pci-quirks.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions
memory region will be marked as reserved in guest E820 table.
We don't need to take care of GGMS, as the accesses to GGMS from HW bypass
IOMMU.
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/pci-quirks.c | 83 ++--
1 file change
This patch introduces device descriptions for Intel platforms. Most of
the Intel device definitions come from i915.
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/Makefile.objs| 2 +-
hw/vfio/intel-platform.c | 366 +++
hw/vfio
This patch introduces device descriptions for Intel platforms. Most of
the Intel device definitions come from i915.
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/Makefile.objs| 2 +-
hw/vfio/intel-platform.c | 366 +++
hw/vfio
Initialize IGD quirks a bit earlier since we're going to support IGD
stolen memory under both primary mode (legacy mode) and secondary mode
and we need one extra memory region from IGD quirks.
Suggested-by: Xiong Zhang
Signed-off-by: Zhi Wang
---
hw/vfio/pci-quirks.c
form definitions and clears some old funtions
and definitions.
Zhi Wang (6):
vfio: Add Intel platform definitions
vfio: Setup IGD quirks earlier
vfio: Setup IGD stolen memory
vfio: Refine GGTT clearing
vfio: Remove extra quirks and old definitions
vfio: Setup IGD stolen memory under seco
Hi,
I am trying to test the ivshmem in KVM. The shared memory without
server works. But I can not find the ivshmem-server. The server pulled
from http://www.gitorious.org/nahanni does not seem to work with the
ivshmem implementation in qemu.git (outdated?). Could any one please
kindly tell me how
Hi,
I am trying to test the ivshmem in KVM. The shared memory without
server works. But I can not
find the ivshmem-server. The server pulled from
http://www.gitorious.org/nahanni does not seem
to work with the ivshmem implementation in qemu.git (outdated?). Could
any one please kindly
tell me how
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